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Wang, Yi
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Publications (10 of 154) Show all publications
Feng, Z., Guan, N., Lv, M., Liu, W., Deng, Q., Liu, X. & Wang, Y. (2020). Efficient drone hijacking detection using two-step GA-XGBoost. Journal of systems architecture, 103, Article ID 101694.
Open this publication in new window or tab >>Efficient drone hijacking detection using two-step GA-XGBoost
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2020 (English)In: Journal of systems architecture, ISSN 1383-7621, E-ISSN 1873-6165, Vol. 103, article id 101694Article in journal (Refereed) Published
Abstract [en]

With the fast growth of civilian drones, their security problems meet significant challenges. A commercial drone may be hijacked by Global Positioning System (GPS)-spoofing attacks for illegal activities, such as terrorist attacks. Ideally, comparing positions respectively estimated by GPS and Inertial Navigation System (INS) can detect such attacks, while the results may always get fault because of the accumulated errors over time in INS. Therefore, in this paper, we propose a two-step GA-XGBoost method to detect GPS-spoofing attacks that just uses GPS and Inertial Measurement Unit (IMU) data. However, tunning the proper values of XGBoost parameters directly on the drone to achieve high prediction results consumes lots of resources which would influence the real-time performance of the drone. The proposed method separates the training phase into offboard step and onboard step. In offboard step, model is first trained by flight logs, and the training parameter values are automatically tuned by Genetic Algorithm (GA). Once the offboard model is trained, it could be uploaded to drones. To adapt our method to drones with different types of sensors and improve the correctness of prediction results, in onboard step, the model is further trained when a drone starts a mission. After onboard training finishes, the proposed method switches to the prediction mode. Besides, our method does not require any extra onboard hardware. The experiments with a real quadrotor drone also show the detection correctness is 96.3% and 100% in hijacked and non-hijacked cases at each sampling time respectively. Moreover, our method can achieve 100% detection correctness just within 1 s just after the attacks start.

Place, publisher, year, edition, pages
ELSEVIER, 2020
Keywords
Cyber-physical system, UAV, Security, GPS spoofing, Machine learning
National Category
Computer Systems Computer Vision and Robotics (Autonomous Systems)
Identifiers
urn:nbn:se:uu:diva-407612 (URN)10.1016/j.sysarc.2019.101694 (DOI)000515208600001 ()
Available from: 2020-04-01 Created: 2020-04-01 Last updated: 2020-04-01Bibliographically approved
Chen, G., Guan, N., Huang, K. & Wang, Y. (2020). Fault-tolerant real-time tasks scheduling with dynamic fault handling. Journal of systems architecture, 102, Article ID 101688.
Open this publication in new window or tab >>Fault-tolerant real-time tasks scheduling with dynamic fault handling
2020 (English)In: Journal of systems architecture, ISSN 1383-7621, E-ISSN 1873-6165, Vol. 102, article id 101688Article in journal (Refereed) Published
Abstract [en]

Predictable performance when coping with transient failures is of paramount importance in safety-critical real-time systems. Various software fault-tolerant techniques are employed towards this goal among which check-pointing is a relatively cost-effective scheme. In this paper, we propose an efficient fault-tolerant scheduling framework with run-time fault handling protocol, where criticality levels can be adaptively inserted for fault handling according to run-time fault workload. In contrast to prior works which apply with task re-execution strategy, the proposed framework adaptively determines on-demand re-executions only on the faulty checkpoint segments, rather than on the whole job. Towards this, a unified overrun handling protocol is developed to handle fault recovery adaptively to avoid over-provisioning of resources. In addition, we develop an off-line schedulability analysis technique for the proposed scheduling algorithm. The simulation results show that our fault-tolerant scheduling framework can bring up to 81% improvement in supporting low-criticality service without sacrifice in the MC-schedulability compared with the existing techniques.

Place, publisher, year, edition, pages
ELSEVIER, 2020
Keywords
Fault-tolerant scheduling, Run-time fault handling, Check-pointing, Safety-critical real-time system
National Category
Computer Engineering
Identifiers
urn:nbn:se:uu:diva-407136 (URN)10.1016/j.sysarc.2019.101688 (DOI)000512220500008 ()
Available from: 2020-03-19 Created: 2020-03-19 Last updated: 2020-03-19Bibliographically approved
Feng, Z., Guan, N., Lv, M., Liu, W., Deng, Q., Liu, X. & Wang, Y. (2019). An Efficient UAV Hijacking Detection Method Using Onboard Inertial Measurement Unit. ACM Transactions on Embedded Computing Systems, 17(6), Article ID 96.
Open this publication in new window or tab >>An Efficient UAV Hijacking Detection Method Using Onboard Inertial Measurement Unit
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2019 (English)In: ACM Transactions on Embedded Computing Systems, ISSN 1539-9087, E-ISSN 1558-3465, Vol. 17, no 6, article id 96Article in journal (Refereed) Published
Abstract [en]

With the fast growth of civil drones, their security problems meet significant challenges. A commercial drone may be hijacked by a GPS-spoofing attack for illegal activities, such as terrorist attacks. The target of this article is to develop a technique that only uses onboard gyroscopes to determine whether a drone has been hijacked. Ideally, GPS data and the angular velocities measured by gyroscopes can be used to estimate the acceleration of a drone, which can be further compared with the measurement of the accelerometer to detect whether a drone has been hijacked. However, the detection results may not always be accurate due to some calculation and measurement errors, especially when no hijacking occurs in curve trajectory situations. To overcome this, in this article, we propose a novel and simple method to detect hijacking only based on gyroscopes' measurements and GPS data, without using any accelerometer in the detection procedure. The computational complexity of our method is very low, which is suitable to be implemented in the drones with micro-controllers. On the other hand, the proposed method does not rely on any accelerometer to detect attacks, which means it receives less information in the detection procedure and may reduce the results accuracy in some special situations. While the previous method can compensate for this flaw, the high detection results also can be guaranteed by using the above two methods. Experiments with a quad-rotor drone are conducted to show the effectiveness of the proposed method and the combination method.

Place, publisher, year, edition, pages
ASSOC COMPUTING MACHINERY, 2019
Keywords
Cyber physical system, unmanned aerial vehicle, GPS spoofing
National Category
Computer Vision and Robotics (Autonomous Systems)
Identifiers
urn:nbn:se:uu:diva-377366 (URN)10.1145/3289390 (DOI)000457135500006 ()
Available from: 2019-02-19 Created: 2019-02-19 Last updated: 2019-02-19Bibliographically approved
Liu, Y., Wei, Y. & Wang, Y. (2019). Depth from defocus (DFD) based on VFISTA optimization algorithm in micro/nanometer vision. Cluster Computing, 22, 1459-1467
Open this publication in new window or tab >>Depth from defocus (DFD) based on VFISTA optimization algorithm in micro/nanometer vision
2019 (English)In: Cluster Computing, ISSN 1386-7857, E-ISSN 1573-7543, Vol. 22, p. 1459-1467Article in journal (Refereed) Published
Abstract [en]

In the three-dimensional (3D) morphological reconstruction of micro/nano-scale vision, the global depth from defocus algorithm (DFD) transforms the depth information of the scene into a dynamic optimization problem to solve. In order to improve the problem of dynamic optimization in the recovery process of global DFD, a variable-step-size fast iterative shrinkage-thresholding algorithm (VFISTA) is proposed. The traditional iterative shrinkage-thresholding algorithm (ISTA) is often used to solve this dynamic optimization problem in the global DFD method. The ISTA algorithm is an extension of the gradient descent method, which is close to the minimal value point of the optimization process, and the convergence speed is slow. What is more, the ISTA algorithm uses fixed step length in the iterative process, The search direction tend to be "orthogonal", prone to "saw tooth" phenomenon, so close to the minimum point when the convergence rate is slower. First, the VFISTA algorithm joins the acceleration operator on the basis of the ISTA algorithm. Further, it combines linear search method to find the optimal iteration length, and changes the limit of the ISTA algorithm step fixed. Finally, it is applied to the depth measurement of defocus scene in micro/nanometer scale vision. The experimental results show that the proposed fast depth from defocus algorithm based on VFISTA has faster convergent speed. Moreover, the precision of the measurement is obviously improved in micro/nanometer scale vision.

Place, publisher, year, edition, pages
SPRINGER, 2019
Keywords
Micro, nanometer vision, Depth from defocus algorithm (DFD), Dynamic optimization, Acceleration operator, Linear search
National Category
Computer Sciences Computational Mathematics
Identifiers
urn:nbn:se:uu:diva-393756 (URN)10.1007/s10586-018-1810-2 (DOI)000480653200123 ()
Available from: 2019-10-18 Created: 2019-10-18 Last updated: 2019-10-18Bibliographically approved
Du, H., Zhang, W., Guan, N. & Wang, Y. (2019). Scope-aware data cache analysis for OpenMP programs on multi-core processors. Journal of systems architecture, 98, 443-452
Open this publication in new window or tab >>Scope-aware data cache analysis for OpenMP programs on multi-core processors
2019 (English)In: Journal of systems architecture, ISSN 1383-7621, E-ISSN 1873-6165, Vol. 98, p. 443-452Article in journal (Refereed) Published
Abstract [en]

OpenMP is the de facto standard parallel programming framework on shared memory architectures, which is not only widely used in general and high-performance computing but also draws increasing interests for real-time embedded systems. Choosing the appropriate assignment of loop iterations to threads is one of the most critical decisions when parallelizing loops, especially considering the large impact by caches behaviors to the program execution time. In this paper, we study data cache analysis for OpenMP programs with parallel loops. We first present a method considering the impact of the schedule clause in OpenMP programs on cache behavior. We capture the dynamic behavior of memory access by computing its temporal scope (the loop iterations where a given memory block is accessed for a given data reference) during address analysis. Based on the ACS representation, we present a temporal scope aware data cache miss calculation technique. Through the experimental result, we propose a convenient way to choose an appropriate parallelization scheme for OpenMP programs.

Place, publisher, year, edition, pages
ELSEVIER, 2019
Keywords
OpenMP, Multicores, Parallelism computing, Cache analysis
National Category
Computer Systems
Identifiers
urn:nbn:se:uu:diva-395700 (URN)10.1016/j.sysarc.2019.04.001 (DOI)000487166300034 ()
Available from: 2019-10-23 Created: 2019-10-23 Last updated: 2019-10-23Bibliographically approved
Abdullah, J., Dai, G. & Wang, Y. (2019). Worst-Case Cause-Effect Reaction Latency in Systems with Non-Blocking Communication. In: Design, Automation & Test in Europe Conference & Exhibition: DATE 2019. Paper presented at DATE 2019, March 25–29, Florence, Italy (pp. 1625-1630). IEEE
Open this publication in new window or tab >>Worst-Case Cause-Effect Reaction Latency in Systems with Non-Blocking Communication
2019 (English)In: Design, Automation & Test in Europe Conference & Exhibition: DATE 2019, IEEE, 2019, p. 1625-1630Conference paper, Published paper (Refereed)
Abstract [en]

In real-time embedded systems, a system functionality is often implemented using a data-flow chain over a set of communicating tasks. A critical non-functional requirement in such systems is to restrict the amount of time, i.e. cause-effect latency, for an input to impact its corresponding output. The problem of estimating the worst-case cause-effect latency is well-studied in the context of blocking inter-task communication. Recent research results show that non-blocking communication preserving functional semantics is critical for the model-based design of dynamically updatable systems. In this paper, we study the worst-case cause-effect reaction latency estimation problem in the context of non-blocking inter-task communication. We present a computationally efficient algorithm that tightly over-approximates the exact worst-case reaction latency in cause-effect data-flow chains.

Place, publisher, year, edition, pages
IEEE, 2019
National Category
Computer Sciences
Identifiers
urn:nbn:se:uu:diva-389931 (URN)10.23919/DATE.2019.8715264 (DOI)000470666100301 ()978-3-9819263-2-3 (ISBN)
Conference
DATE 2019, March 25–29, Florence, Italy
Available from: 2019-08-01 Created: 2019-08-01 Last updated: 2019-10-07Bibliographically approved
Sun, J., Guan, N., Jiang, X., Chang, S., Guo, Z., Deng, Q. & Wang, Y. (2018). A Capacity Augmentation Bound for Real-Time Constrained-Deadline Parallel Tasks Under GEDF. Paper presented at Embedded Syst Week (ESWEEK) / Int Conf on Compilers, Architecture, and Synthesis for Embedded Syst (CASES) / Int Conf on Hardware/Software Codesign and Syst Synthesis (CODES+ISSS) / ACM SIGBED Int Conf on Embedded Software (EMSOFT), MAR 27-APR 03, 2018, Torino, ITALY. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 37(11), 2200-2211
Open this publication in new window or tab >>A Capacity Augmentation Bound for Real-Time Constrained-Deadline Parallel Tasks Under GEDF
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2018 (English)In: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, ISSN 0278-0070, E-ISSN 1937-4151, Vol. 37, no 11, p. 2200-2211Article in journal (Refereed) Published
Abstract [en]

Capacity augmentation bound is a widely used quantitative metric in theoretical studies of schedulability analysis for directed acyclic graph (DAG) parallel real-time tasks, which not only quantifies the suboptimality of the scheduling algorithms, but also serves as a simple linear-time schedulability test. Earlier studies on capacity augmentation bounds of the sporadic DAG task model were either restricted to a single DAG task or a set of tasks with implicit deadlines. In this paper, we consider parallel tasks with constrained deadlines under global earliest deadline first policy. We first show that it is impossible to obtain a constant bound for our problem setting, and derive both lower and upper bounds of the capacity augmentation bound as a function with respect to the maximum ratio of task period to deadline. Our upper bound is at most 1.47 times larger than the optimal one. We conduct experiments to compare the acceptance ratio of our capacity augmentation bound with the existing schedulability test also having linear-time complexity. The results show that our capacity augmentation bound significantly outperforms the existing linear-time schedulability test under different parameter settings.

Keywords
Capacity augmentation bound, directed acyclic graph (DAG), global earliest deadline first (GEDF), parallel tasks, real-time scheduling, schedulability analysis
National Category
Computer Sciences
Identifiers
urn:nbn:se:uu:diva-370013 (URN)10.1109/TCAD.2018.2857362 (DOI)000447854500003 ()
Conference
Embedded Syst Week (ESWEEK) / Int Conf on Compilers, Architecture, and Synthesis for Embedded Syst (CASES) / Int Conf on Hardware/Software Codesign and Syst Synthesis (CODES+ISSS) / ACM SIGBED Int Conf on Embedded Software (EMSOFT), MAR 27-APR 03, 2018, Torino, ITALY
Available from: 2019-01-07 Created: 2019-01-07 Last updated: 2019-01-07Bibliographically approved
Chen, G., Guan, N., Hu, B. & Wang, Y. (2018). EDF-VD Scheduling of Flexible Mixed-Criticality System With Multiple-Shot Transitions. Paper presented at Embedded Syst Week (ESWEEK) / Int Conf on Compilers, Architecture, and Synthesis for Embedded Syst (CASES) / Int Conf on Hardware/Software Codesign and Syst Synthesis (CODES+ISSS) / ACM SIGBED Int Conf on Embedded Software (EMSOFT), MAR 27-APR 03, 2018, Torino, ITALY. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 37(11), 2393-2403
Open this publication in new window or tab >>EDF-VD Scheduling of Flexible Mixed-Criticality System With Multiple-Shot Transitions
2018 (English)In: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, ISSN 0278-0070, E-ISSN 1937-4151, Vol. 37, no 11, p. 2393-2403Article in journal (Refereed) Published
Abstract [en]

The existing mixed-criticality (MC) real-time task models assume that once any high-criticality task overruns, all high-criticality jobs execute up to their most pessimistic WCET estimations simultaneously in a one-shot manner. This is very pessimistic in the sense of unnecessary resource overbooking. In this paper, we propose a more generalized mixed-critical real-time task model, called flexible MC model with multiple-shot transitions (FMC-MST), to address this problem. In FMC-MST, high-criticality tasks can transit multiple intermediate levels to handle less pessimistic overruns independently and to nonuni-formly scale the deadline on each level. We develop a run-time schedulability analysis for FMC-MST under EDF-VD scheduling, in which a better tradeoff between the penalties of low-criticality tasks and the overruns of high-criticality tasks is achieved to improve the service quality of low-criticality tasks. We also develop a resource optimization technique to find resource-efficient level-insertion configurations for FMC-MST task systems under MC timing constraints. Experiments demonstrate the effectiveness of FMC-MST compared with the state-of-the-art techniques.

Keywords
EDF-VD scheduling, flexible mixed-criticality (FMC) system, multiple-shot transitions
National Category
Computer Sciences
Identifiers
urn:nbn:se:uu:diva-370014 (URN)10.1109/TCAD.2018.2857359 (DOI)000447854500020 ()
Conference
Embedded Syst Week (ESWEEK) / Int Conf on Compilers, Architecture, and Synthesis for Embedded Syst (CASES) / Int Conf on Hardware/Software Codesign and Syst Synthesis (CODES+ISSS) / ACM SIGBED Int Conf on Embedded Software (EMSOFT), MAR 27-APR 03, 2018, Torino, ITALY
Available from: 2019-01-07 Created: 2019-01-07 Last updated: 2019-01-07Bibliographically approved
An, J., Zhan, N., Li, X., Zhang, M. & Wang, Y. (2018). Model Checking Bounded Continuous-time Extended Linear Duration Invariants. In: HSCC 2018: Proceedings of the 21st International Conference on Hybrid Systems: Computation and Control (HSCC). Paper presented at 21st ACM International Conference on Hybrid Systems - Computation and Control (HSCC), Porto, Portugal, April 11-13, 2018 (pp. 81-90). ASSOC COMPUTING MACHINERY
Open this publication in new window or tab >>Model Checking Bounded Continuous-time Extended Linear Duration Invariants
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2018 (English)In: HSCC 2018: Proceedings of the 21st International Conference on Hybrid Systems: Computation and Control (HSCC), ASSOC COMPUTING MACHINERY , 2018, p. 81-90Conference paper, Published paper (Refereed)
Abstract [en]

Extended Linear Duration Invariants (ELDI), an important subset of Duration Calculus, extends well-studied Linear Duration Invariants with logical connectives and the chop modality. It is known that the model checking problem of ELDI is undecidable with both the standard continuous-time and discrete-time semantics [12, 13], but it turns out to be decidable if only bounded execution fragments of timed automata are concerned in the context of the discrete-time semantics [36]. In this paper, we prove that this problem is still decidable in the continuous-time semantics, although it is well-known that model-checking Duration Calculus with the continuous-time semantics is much more complicated than the one with the discrete-time semantics. This is achieved by reduction to the validity of Quantified Linear Real Arithmetic (QLRA). Some examples are provided to illustrate the efficiency of our approach.

Place, publisher, year, edition, pages
ASSOC COMPUTING MACHINERY, 2018
Keywords
Model Checking, Duration Calculus, ELDI, Timed Automata, Quantified Linear Real Arithmetic
National Category
Computer Sciences
Identifiers
urn:nbn:se:uu:diva-390243 (URN)10.1145/3178126.3178147 (DOI)000474781600009 ()
Conference
21st ACM International Conference on Hybrid Systems - Computation and Control (HSCC), Porto, Portugal, April 11-13, 2018
Available from: 2019-08-07 Created: 2019-08-07 Last updated: 2019-08-07Bibliographically approved
Abdullah, J., Dai, G., Mohaqeqi, M. & Yi, W. (2018). Schedulability Analysis and Software Synthesis for Graph-Based Task Models with Resource Sharing. In: Proc. 24th Real-Time and Embedded Technology and Applications Symposium: . Paper presented at RTAS 2018, April 11–13, Porto, Portugal (pp. 261-270). IEEE Computer Society
Open this publication in new window or tab >>Schedulability Analysis and Software Synthesis for Graph-Based Task Models with Resource Sharing
2018 (English)In: Proc. 24th Real-Time and Embedded Technology and Applications Symposium, IEEE Computer Society, 2018, p. 261-270Conference paper, Published paper (Refereed)
Place, publisher, year, edition, pages
IEEE Computer Society, 2018
National Category
Computer Systems
Identifiers
urn:nbn:se:uu:diva-364848 (URN)10.1109/RTAS.2018.00034 (DOI)000443421100028 ()978-1-5386-5295-4 (ISBN)
Conference
RTAS 2018, April 11–13, Porto, Portugal
Available from: 2018-11-05 Created: 2018-11-05 Last updated: 2018-11-12Bibliographically approved
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