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Wang, Yi
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Publications (10 of 150) Show all publications
Feng, Z., Guan, N., Lv, M., Liu, W., Deng, Q., Liu, X. & Wang, Y. (2019). An Efficient UAV Hijacking Detection Method Using Onboard Inertial Measurement Unit. ACM Transactions on Embedded Computing Systems, 17(6), Article ID 96.
Open this publication in new window or tab >>An Efficient UAV Hijacking Detection Method Using Onboard Inertial Measurement Unit
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2019 (English)In: ACM Transactions on Embedded Computing Systems, ISSN 1539-9087, E-ISSN 1558-3465, Vol. 17, no 6, article id 96Article in journal (Refereed) Published
Abstract [en]

With the fast growth of civil drones, their security problems meet significant challenges. A commercial drone may be hijacked by a GPS-spoofing attack for illegal activities, such as terrorist attacks. The target of this article is to develop a technique that only uses onboard gyroscopes to determine whether a drone has been hijacked. Ideally, GPS data and the angular velocities measured by gyroscopes can be used to estimate the acceleration of a drone, which can be further compared with the measurement of the accelerometer to detect whether a drone has been hijacked. However, the detection results may not always be accurate due to some calculation and measurement errors, especially when no hijacking occurs in curve trajectory situations. To overcome this, in this article, we propose a novel and simple method to detect hijacking only based on gyroscopes' measurements and GPS data, without using any accelerometer in the detection procedure. The computational complexity of our method is very low, which is suitable to be implemented in the drones with micro-controllers. On the other hand, the proposed method does not rely on any accelerometer to detect attacks, which means it receives less information in the detection procedure and may reduce the results accuracy in some special situations. While the previous method can compensate for this flaw, the high detection results also can be guaranteed by using the above two methods. Experiments with a quad-rotor drone are conducted to show the effectiveness of the proposed method and the combination method.

Place, publisher, year, edition, pages
ASSOC COMPUTING MACHINERY, 2019
Keywords
Cyber physical system, unmanned aerial vehicle, GPS spoofing
National Category
Computer Vision and Robotics (Autonomous Systems)
Identifiers
urn:nbn:se:uu:diva-377366 (URN)10.1145/3289390 (DOI)000457135500006 ()
Available from: 2019-02-19 Created: 2019-02-19 Last updated: 2019-02-19Bibliographically approved
Abdullah, J., Dai, G. & Wang, Y. (2019). Worst-Case Cause-Effect Reaction Latency in Systems with Non-Blocking Communication. In: Design, Automation & Test in Europe Conference & Exhibition: DATE 2019. Paper presented at DATE 2019, March 25–29, Florence, Italy (pp. 1625-1630). IEEE
Open this publication in new window or tab >>Worst-Case Cause-Effect Reaction Latency in Systems with Non-Blocking Communication
2019 (English)In: Design, Automation & Test in Europe Conference & Exhibition: DATE 2019, IEEE, 2019, p. 1625-1630Conference paper, Published paper (Refereed)
Abstract [en]

In real-time embedded systems, a system functionality is often implemented using a data-flow chain over a set of communicating tasks. A critical non-functional requirement in such systems is to restrict the amount of time, i.e. cause-effect latency, for an input to impact its corresponding output. The problem of estimating the worst-case cause-effect latency is well-studied in the context of blocking inter-task communication. Recent research results show that non-blocking communication preserving functional semantics is critical for the model-based design of dynamically updatable systems. In this paper, we study the worst-case cause-effect reaction latency estimation problem in the context of non-blocking inter-task communication. We present a computationally efficient algorithm that tightly over-approximates the exact worst-case reaction latency in cause-effect data-flow chains.

Place, publisher, year, edition, pages
IEEE, 2019
National Category
Computer Sciences
Identifiers
urn:nbn:se:uu:diva-389931 (URN)10.23919/DATE.2019.8715264 (DOI)000470666100301 ()978-3-9819263-2-3 (ISBN)
Conference
DATE 2019, March 25–29, Florence, Italy
Available from: 2019-08-01 Created: 2019-08-01 Last updated: 2019-10-07Bibliographically approved
Sun, J., Guan, N., Jiang, X., Chang, S., Guo, Z., Deng, Q. & Wang, Y. (2018). A Capacity Augmentation Bound for Real-Time Constrained-Deadline Parallel Tasks Under GEDF. Paper presented at Embedded Syst Week (ESWEEK) / Int Conf on Compilers, Architecture, and Synthesis for Embedded Syst (CASES) / Int Conf on Hardware/Software Codesign and Syst Synthesis (CODES+ISSS) / ACM SIGBED Int Conf on Embedded Software (EMSOFT), MAR 27-APR 03, 2018, Torino, ITALY. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 37(11), 2200-2211
Open this publication in new window or tab >>A Capacity Augmentation Bound for Real-Time Constrained-Deadline Parallel Tasks Under GEDF
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2018 (English)In: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, ISSN 0278-0070, E-ISSN 1937-4151, Vol. 37, no 11, p. 2200-2211Article in journal (Refereed) Published
Abstract [en]

Capacity augmentation bound is a widely used quantitative metric in theoretical studies of schedulability analysis for directed acyclic graph (DAG) parallel real-time tasks, which not only quantifies the suboptimality of the scheduling algorithms, but also serves as a simple linear-time schedulability test. Earlier studies on capacity augmentation bounds of the sporadic DAG task model were either restricted to a single DAG task or a set of tasks with implicit deadlines. In this paper, we consider parallel tasks with constrained deadlines under global earliest deadline first policy. We first show that it is impossible to obtain a constant bound for our problem setting, and derive both lower and upper bounds of the capacity augmentation bound as a function with respect to the maximum ratio of task period to deadline. Our upper bound is at most 1.47 times larger than the optimal one. We conduct experiments to compare the acceptance ratio of our capacity augmentation bound with the existing schedulability test also having linear-time complexity. The results show that our capacity augmentation bound significantly outperforms the existing linear-time schedulability test under different parameter settings.

Keywords
Capacity augmentation bound, directed acyclic graph (DAG), global earliest deadline first (GEDF), parallel tasks, real-time scheduling, schedulability analysis
National Category
Computer Sciences
Identifiers
urn:nbn:se:uu:diva-370013 (URN)10.1109/TCAD.2018.2857362 (DOI)000447854500003 ()
Conference
Embedded Syst Week (ESWEEK) / Int Conf on Compilers, Architecture, and Synthesis for Embedded Syst (CASES) / Int Conf on Hardware/Software Codesign and Syst Synthesis (CODES+ISSS) / ACM SIGBED Int Conf on Embedded Software (EMSOFT), MAR 27-APR 03, 2018, Torino, ITALY
Available from: 2019-01-07 Created: 2019-01-07 Last updated: 2019-01-07Bibliographically approved
Chen, G., Guan, N., Hu, B. & Wang, Y. (2018). EDF-VD Scheduling of Flexible Mixed-Criticality System With Multiple-Shot Transitions. Paper presented at Embedded Syst Week (ESWEEK) / Int Conf on Compilers, Architecture, and Synthesis for Embedded Syst (CASES) / Int Conf on Hardware/Software Codesign and Syst Synthesis (CODES+ISSS) / ACM SIGBED Int Conf on Embedded Software (EMSOFT), MAR 27-APR 03, 2018, Torino, ITALY. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 37(11), 2393-2403
Open this publication in new window or tab >>EDF-VD Scheduling of Flexible Mixed-Criticality System With Multiple-Shot Transitions
2018 (English)In: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, ISSN 0278-0070, E-ISSN 1937-4151, Vol. 37, no 11, p. 2393-2403Article in journal (Refereed) Published
Abstract [en]

The existing mixed-criticality (MC) real-time task models assume that once any high-criticality task overruns, all high-criticality jobs execute up to their most pessimistic WCET estimations simultaneously in a one-shot manner. This is very pessimistic in the sense of unnecessary resource overbooking. In this paper, we propose a more generalized mixed-critical real-time task model, called flexible MC model with multiple-shot transitions (FMC-MST), to address this problem. In FMC-MST, high-criticality tasks can transit multiple intermediate levels to handle less pessimistic overruns independently and to nonuni-formly scale the deadline on each level. We develop a run-time schedulability analysis for FMC-MST under EDF-VD scheduling, in which a better tradeoff between the penalties of low-criticality tasks and the overruns of high-criticality tasks is achieved to improve the service quality of low-criticality tasks. We also develop a resource optimization technique to find resource-efficient level-insertion configurations for FMC-MST task systems under MC timing constraints. Experiments demonstrate the effectiveness of FMC-MST compared with the state-of-the-art techniques.

Keywords
EDF-VD scheduling, flexible mixed-criticality (FMC) system, multiple-shot transitions
National Category
Computer Sciences
Identifiers
urn:nbn:se:uu:diva-370014 (URN)10.1109/TCAD.2018.2857359 (DOI)000447854500020 ()
Conference
Embedded Syst Week (ESWEEK) / Int Conf on Compilers, Architecture, and Synthesis for Embedded Syst (CASES) / Int Conf on Hardware/Software Codesign and Syst Synthesis (CODES+ISSS) / ACM SIGBED Int Conf on Embedded Software (EMSOFT), MAR 27-APR 03, 2018, Torino, ITALY
Available from: 2019-01-07 Created: 2019-01-07 Last updated: 2019-01-07Bibliographically approved
An, J., Zhan, N., Li, X., Zhang, M. & Wang, Y. (2018). Model Checking Bounded Continuous-time Extended Linear Duration Invariants. In: HSCC 2018: Proceedings of the 21st International Conference on Hybrid Systems: Computation and Control (HSCC). Paper presented at 21st ACM International Conference on Hybrid Systems - Computation and Control (HSCC), Porto, Portugal, April 11-13, 2018 (pp. 81-90). ASSOC COMPUTING MACHINERY
Open this publication in new window or tab >>Model Checking Bounded Continuous-time Extended Linear Duration Invariants
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2018 (English)In: HSCC 2018: Proceedings of the 21st International Conference on Hybrid Systems: Computation and Control (HSCC), ASSOC COMPUTING MACHINERY , 2018, p. 81-90Conference paper, Published paper (Refereed)
Abstract [en]

Extended Linear Duration Invariants (ELDI), an important subset of Duration Calculus, extends well-studied Linear Duration Invariants with logical connectives and the chop modality. It is known that the model checking problem of ELDI is undecidable with both the standard continuous-time and discrete-time semantics [12, 13], but it turns out to be decidable if only bounded execution fragments of timed automata are concerned in the context of the discrete-time semantics [36]. In this paper, we prove that this problem is still decidable in the continuous-time semantics, although it is well-known that model-checking Duration Calculus with the continuous-time semantics is much more complicated than the one with the discrete-time semantics. This is achieved by reduction to the validity of Quantified Linear Real Arithmetic (QLRA). Some examples are provided to illustrate the efficiency of our approach.

Place, publisher, year, edition, pages
ASSOC COMPUTING MACHINERY, 2018
Keywords
Model Checking, Duration Calculus, ELDI, Timed Automata, Quantified Linear Real Arithmetic
National Category
Computer Sciences
Identifiers
urn:nbn:se:uu:diva-390243 (URN)10.1145/3178126.3178147 (DOI)000474781600009 ()
Conference
21st ACM International Conference on Hybrid Systems - Computation and Control (HSCC), Porto, Portugal, April 11-13, 2018
Available from: 2019-08-07 Created: 2019-08-07 Last updated: 2019-08-07Bibliographically approved
Abdullah, J., Dai, G., Mohaqeqi, M. & Yi, W. (2018). Schedulability Analysis and Software Synthesis for Graph-Based Task Models with Resource Sharing. In: Proc. 24th Real-Time and Embedded Technology and Applications Symposium: . Paper presented at RTAS 2018, April 11–13, Porto, Portugal (pp. 261-270). IEEE Computer Society
Open this publication in new window or tab >>Schedulability Analysis and Software Synthesis for Graph-Based Task Models with Resource Sharing
2018 (English)In: Proc. 24th Real-Time and Embedded Technology and Applications Symposium, IEEE Computer Society, 2018, p. 261-270Conference paper, Published paper (Refereed)
Place, publisher, year, edition, pages
IEEE Computer Society, 2018
National Category
Computer Systems
Identifiers
urn:nbn:se:uu:diva-364848 (URN)10.1109/RTAS.2018.00034 (DOI)000443421100028 ()978-1-5386-5295-4 (ISBN)
Conference
RTAS 2018, April 11–13, Porto, Portugal
Available from: 2018-11-05 Created: 2018-11-05 Last updated: 2018-11-12Bibliographically approved
Wang, Y. (2018). The Cause-Effect Latency Problem in Real-Time Systems. In: Howar, F Barnat, J (Ed.), Formal Methods For Industrial Critical Systems, FMICS 2018: . Paper presented at 23rd International Conference on Formal Methods for Industrial Critical Systems (FMICS), SEP 03-04, 2018, Natl Univ Ireland Maynooth, Maynooth, IRELAND (pp. XIII-XIII). SPRINGER INTERNATIONAL PUBLISHING AG
Open this publication in new window or tab >>The Cause-Effect Latency Problem in Real-Time Systems
2018 (English)In: Formal Methods For Industrial Critical Systems, FMICS 2018 / [ed] Howar, F Barnat, J, SPRINGER INTERNATIONAL PUBLISHING AG , 2018, p. XIII-XIIIConference paper, Published paper (Refereed)
Place, publisher, year, edition, pages
SPRINGER INTERNATIONAL PUBLISHING AG, 2018
Series
Lecture Notes in Computer Science, ISSN 0302-9743, E-ISSN 1611-3349 ; 11119
National Category
Computer Sciences
Identifiers
urn:nbn:se:uu:diva-391438 (URN)000477763200002 ()978-3-030-00244-2 (ISBN)978-3-030-00243-5 (ISBN)
Conference
23rd International Conference on Formal Methods for Industrial Critical Systems (FMICS), SEP 03-04, 2018, Natl Univ Ireland Maynooth, Maynooth, IRELAND
Available from: 2019-10-03 Created: 2019-10-03 Last updated: 2019-10-03Bibliographically approved
Chen, G., Guan, N., Liu, D., He, Q., Huang, K., Stefanov, T. & Wang, Y. (2018). Utilization-Based Scheduling of Flexible Mixed-Criticality Real-Time Tasks. I.E.E.E. transactions on computers (Print), 67(4), 543-558
Open this publication in new window or tab >>Utilization-Based Scheduling of Flexible Mixed-Criticality Real-Time Tasks
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2018 (English)In: I.E.E.E. transactions on computers (Print), ISSN 0018-9340, E-ISSN 1557-9956, Vol. 67, no 4, p. 543-558Article in journal (Refereed) Published
Abstract [en]

Mixed-criticality models are an emerging paradigm for the design of real-time systems because of their significantly improved resource efficiency. However, formal mixed-criticality models have traditionally been characterized by two impractical assumptions: once any high-criticality task overruns, all low-criticality tasks are suspended and all other high-criticality tasks are assumed to exhibit high-criticality behaviors at the same time. In this paper, we propose a more realistic mixed-criticality model, called the flexible mixed-criticality (FMC) model, in which these two issues are addressed in a combined manner. In this new model, only the overrun task itself is assumed to exhibit high-criticality behavior, while other high-criticality tasks remain in the same mode as before. The guaranteed service levels of low-criticality tasks are gracefully degraded with the overruns of high-criticality tasks. We derive a utilization-based technique to analyze the schedulability of this new mixed-criticality model under EDF-VD scheduling. During run time, the proposed test condition serves an important criterion for dynamic service level tuning, by means of which the maximum available execution budget for low-criticality tasks can be directly determined with minimal overhead while guaranteeing mixed-criticality schedulability. Experiments demonstrate the effectiveness of the FMC scheme compared with state-of-the-art techniques.

Place, publisher, year, edition, pages
IEEE COMPUTER SOC, 2018
Keywords
EDF-VD scheduling, flexible mixed-criticality system, utilization-based analysis
National Category
Computer Sciences
Identifiers
urn:nbn:se:uu:diva-350728 (URN)10.1109/TC.2017.2763133 (DOI)000427420800007 ()
Available from: 2018-05-17 Created: 2018-05-17 Last updated: 2018-05-17Bibliographically approved
Mohaqeqi, M., Abdullah, J. & Yi, W. (2017). An executable semantics for synchronous task graphs: From SDRT to Ada. In: Reliable Software Technologies — Ada-Europe 2017: . Paper presented at 22nd Ada-Europe International Conference on Reliable Software Technologies (Ada-Europe)2017, June 12–16, Vienna, Austria. (pp. 137-152). Springer, 10300
Open this publication in new window or tab >>An executable semantics for synchronous task graphs: From SDRT to Ada
2017 (English)In: Reliable Software Technologies — Ada-Europe 2017, Springer, 2017, Vol. 10300, p. 137-152Conference paper, Published paper (Refereed)
Abstract [en]

We study a graph-based real-time task model in which inter-task synchronization can be specified through a rendezvous mechanism. Previously, efficient methods have been proposed for timing analysis of the corresponding task sets. In this paper, we first formally specify an operational semantics for the model. Next, we describe a method for Ada code generation for a set of such task graphs. We also specify extensions of the approach to cover a notion of broadcasting, as well as global inter-release separation time of real-time jobs. We have implemented the proposed method in a graphical tool which facilitates a model-based design and implementation of real-time software.

Place, publisher, year, edition, pages
Springer, 2017
Series
Lecture Notes in Computer Science ; 10300
National Category
Embedded Systems
Identifiers
urn:nbn:se:uu:diva-326691 (URN)10.1007/978-3-319-60588-3_9 (DOI)000433224100009 ()978-3-319-60587-6 (ISBN)
Conference
22nd Ada-Europe International Conference on Reliable Software Technologies (Ada-Europe)2017, June 12–16, Vienna, Austria.
Projects
UPMARC
Available from: 2017-05-30 Created: 2017-07-22 Last updated: 2018-09-25Bibliographically approved
Wang, Y., Guan, N., Sun, J., Lv, M., He, Q., He, T. & Wang, Y. (2017). Benchmarking OpenMP Programs for Real-Time Scheduling. In: 2017 IEEE 23Rd International Conference On Embedded And Real-Time Computing Systems And Applications (RTSCA): . Paper presented at 23rd IEEE International Conference on Embedded and Real-Time Computing Systems and Applications (RTCSA), AUG 16-18, 2017, Natl Chiao Tung Univ, Hsinchu, TAIWAN. IEEE Computer Society
Open this publication in new window or tab >>Benchmarking OpenMP Programs for Real-Time Scheduling
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2017 (English)In: 2017 IEEE 23Rd International Conference On Embedded And Real-Time Computing Systems And Applications (RTSCA), IEEE Computer Society, 2017Conference paper, Published paper (Refereed)
Abstract [en]

Real-time systems are shifting from single-core to multi-core processors. Software must be parallelized to fully utilize the computation power of multi-core architecture. OpenMP is a popular parallel programming framework in general and high-performance computing, and recently has drawn a lot of interests in embedded and real-time computing. Much recent work has been done on real-time scheduling of OpenMP-based parallel workload. However, these studies conduct evaluations with randomly generated task systems, which cannot well represent the structure features of OpenMP workload. This paper presents a benchmark suite, ompTGB, to support research on real-time scheduling of OpenMP-based parallel tasks. ompTGB does not only collect realistic OpenMP programs, but also models them into task graphs so that the real-time scheduling researchers can easily understand and use them. We also present a new response time bound for a subset of OpenMP programs and use it to demonstrate the usage of ompTGB.

Place, publisher, year, edition, pages
IEEE Computer Society, 2017
Series
IEEE International Conference on Embedded and Real-Time Computing Systems and Applications, ISSN 1533-2306
Keywords
Real-time systems, Benchmark testing, Tools, Time factors, Processor scheduling, Computer architecture, Hardware
National Category
Computer Systems
Identifiers
urn:nbn:se:uu:diva-351191 (URN)10.1109/RTCSA.2017.8046322 (DOI)000425851000020 ()978-1-5386-1898-1 (ISBN)
Conference
23rd IEEE International Conference on Embedded and Real-Time Computing Systems and Applications (RTCSA), AUG 16-18, 2017, Natl Chiao Tung Univ, Hsinchu, TAIWAN
Available from: 2018-05-21 Created: 2018-05-21 Last updated: 2018-05-21Bibliographically approved
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