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Vallin, Örjan
Publications (10 of 40) Show all publications
Serrano, I. G., Panda, J., Denoel, F., Vallin, Ö., Phuyal, D., Karis, O. & Kamalakar, M. V. (2019). Two-Dimensional Flexible High Diffusive Spin Circuits. Nano letters (Print), 19(2), 666-673
Open this publication in new window or tab >>Two-Dimensional Flexible High Diffusive Spin Circuits
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2019 (English)In: Nano letters (Print), ISSN 1530-6984, E-ISSN 1530-6992, Vol. 19, no 2, p. 666-673Article in journal (Refereed) Published
Abstract [en]

Owing to their unprecedented electronic properties, graphene and two-dimensional (2D) crystals have brought fresh opportunities for advances in planar spintronic devices. Graphene is an ideal medium for spin transport while being an exceptionally resilient material for flexible nanoelectronics. However, these extraordinary traits have never been combined to create flexible graphene spin circuits. Realizing such circuits could lead to bendable strain-spin sensors, as well as a unique platform to explore pure spin current based operations and low-power 2D flexible nanoelectronics. Here, we demonstrate graphene spin circuits on flexible substrates for the first time. Despite the rough topography of the flexible substrates, these circuits prepared with chemical vapor deposited monolayer graphene reveal an efficient room temperature spin transport with distinctively large spin diffusion coefficients ∼0.2 m2 s–1. Compared to earlier graphene devices on Si/SiO2 substrates, such values are up to 20 times larger, leading to one order higher spin signals and an enhanced spin diffusion length ∼10 μm in graphene-based nonlocal spin valves fabricated using industry standard systems. This high performance arising out of a characteristic substrate terrain shows promise of a scalable and flexible platform towards flexible 2D spintronics. Our innovation is a key step for the exploration of strain-dependent 2D spin phenomena and paves the way for flexible graphene spin memory–logic units and planar spin sensors.

Keywords
Flexible graphene spin circuits, flexible graphene spintronics, spin transport in graphene, two-dimensional spintronics, bendable nanoelectronics
National Category
Condensed Matter Physics Other Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:uu:diva-378732 (URN)10.1021/acs.nanolett.8b03520 (DOI)000459222300006 ()30632370 (PubMedID)
Funder
Swedish Research Council, 2016-03278Knut and Alice Wallenberg FoundationStiftelsen Olle Engkvist ByggmästareThe Wenner-Gren Foundation
Note

De 3 första författarna delar förstaförfattarskapet.

Available from: 2019-03-08 Created: 2019-03-08 Last updated: 2020-05-13Bibliographically approved
Banerjee, D., Vallin, Ö., Samani, K. M., Majee, S., Zhang, S.-L., Liu, J. & Zhang, Z.-B. (2018). Elevated thermoelectric figure of merit of n-type amorphous silicon by efficient electrical doping process. Nano Energy, 44, 89-94
Open this publication in new window or tab >>Elevated thermoelectric figure of merit of n-type amorphous silicon by efficient electrical doping process
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2018 (English)In: Nano Energy, ISSN 2211-2855, E-ISSN 2211-3282, Vol. 44, p. 89-94Article in journal (Refereed) Published
Abstract [en]

The currently dominant thermoelectric (TE) materials used in low to medium temperature range contain Tellurium that is rare and mild-toxic. Silicon is earth abundant and environment friendly, but it is characterized by a poor TE efficiency with a low figure of merit, ZT. In this work, we report that ZT of amorphous silicon (a-Si) thin films can be enhanced by 7 orders of magnitude, reaching similar to 0.64 +/- 0.13 at room temperature, by means of arsenic ion implantation followed by low-temperature dopant activation. The dopant introduction employed represents a highly controllable doping technique used in standard silicon technology. It is found that the significant enhancement of ZT achieved is primarily due to a significant improvement of electrical conductivity by doping without crystallization so as to maintain the thermal conductivity and Seebeck coefficient at the level determined by the amorphous state of the silicon films. Our results open up a new route towards enabling a-Si as a prominent TE material for cost-efficient and environment-friendly TE applications at room temperature.

Place, publisher, year, edition, pages
ELSEVIER SCIENCE BV, 2018
Keywords
Thermoelectrics, Amorphous silicon, Electrical conductivity, Electrical doping, Energy harvesting
National Category
Materials Engineering
Identifiers
urn:nbn:se:uu:diva-341565 (URN)10.1016/j.nanoen.2017.11.060 (DOI)000419833900011 ()
Funder
Swedish Research Council, 621-2014-5596Swedish Foundation for Strategic Research , SE13-0061
Available from: 2018-02-12 Created: 2018-02-12 Last updated: 2018-02-27Bibliographically approved
Kovi, K. K., Vallin, Ö., Majdi, S. & Isberg, J. (2015). Inversion in Metal–Oxide–Semiconductor Capacitors on Boron-Doped Diamond. IEEE Electron Device Letters, 36(6), 603-605
Open this publication in new window or tab >>Inversion in Metal–Oxide–Semiconductor Capacitors on Boron-Doped Diamond
2015 (English)In: IEEE Electron Device Letters, ISSN 0741-3106, E-ISSN 1558-0563, Vol. 36, no 6, p. 603-605Article in journal (Refereed) Published
Abstract [en]

For the advancement of diamond-based electronic devices, the fabrication of metal-oxide-semiconductor field-effect transistors (MOSFETs) is crucial, as this device finds applications in numerous fields of power electronics and high-frequency systems. The MOS capacitor forms the basic building block of the MOSFET. In this letter, we describe planar MOS capacitor structures fabricated with atomic layer deposited aluminum oxide as the dielectric on oxygen-terminated boron-doped diamond substrates with different doping levels. Using capacitance-voltage measurements, we have, for the first time, observed inversion behavior in MOS structures on boron-doped diamond, with a doping concentration of 4.1 × 1019/cm3.

National Category
Engineering and Technology
Research subject
Engineering Science with specialization in Electronics; Engineering Science with specialization in Science of Electricity
Identifiers
urn:nbn:se:uu:diva-253954 (URN)10.1109/LED.2015.2423971 (DOI)000355252300025 ()
Available from: 2015-06-04 Created: 2015-06-04 Last updated: 2017-12-04Bibliographically approved
Li, L.-G., Rubino, S., Vallin, Ö. & Olsson, J. (2014). Dynamics of SiO2 Buried Layer Removal from Si-SiO2-Si and Si-SiO2-SiC Bonded Substrates by Annealing in Ar. Journal of Electronic Materials, 43(2), 541-547
Open this publication in new window or tab >>Dynamics of SiO2 Buried Layer Removal from Si-SiO2-Si and Si-SiO2-SiC Bonded Substrates by Annealing in Ar
2014 (English)In: Journal of Electronic Materials, ISSN 0361-5235, E-ISSN 1543-186X, Vol. 43, no 2, p. 541-547Article in journal (Refereed) Published
Abstract [en]

Silicon-on-silicon-carbide substrates could be ideal for high-power and radiofrequency silicon devices. Such hybrid wafers, when made by wafer bonding, contain an intermediate silicon dioxide layer with poor thermal characteristics, which can be removed by high-temperature annealing in an inert atmosphere. To understand the dynamics of this process, removal of 2.4-nm-thick SiO2 layers from Si-SiO2-Si and Si-SiO2-SiC substrates has been studied at temperatures ranging from 1100A degrees C to 1200A degrees C. The substrates were analyzed by transmission electron microscopy, electron energy-loss spectroscopy, secondary-ion mass spectroscopy, and ellipsometry, before and after annealing. For oxide thickness less than 2.4 nm, the activation energy for oxide removal was estimated to be 6.4 eV, being larger than the activation energy reported for removal of thicker oxides (4.1 eV). Under the same conditions, the SiO2 layer became discontinuous. In the time domain, three steps could be distinguished: bulk diffusion, bulk diffusion with void formation, and bulk diffusion with disintegration. The void formation, predominant here, has an energetic cost that could explain the larger activation energy. The oxide remaining after prolonged annealing corresponds to one layer of oxygen atoms.

Place, publisher, year, edition, pages
Springer Berlin/Heidelberg, 2014
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Research subject
Engineering Science with specialization in Materials Science; Engineering Science with specialization in Electronics
Identifiers
urn:nbn:se:uu:diva-209754 (URN)10.1007/s11664-013-2861-z (DOI)000329656700034 ()
Available from: 2013-10-25 Created: 2013-10-25 Last updated: 2017-12-06Bibliographically approved
Mardani, S., Primetzhofer, D., Liljeholm, L., Vallin, Ö., Norström, H. & Olsson, J. (2014). Electrical properties of Ag/Ta and Ag/TaN thin-films. Paper presented at MAM 2013 - Materials for Advanced Metallization; 10-13 March 2013; Leuven, Belgium. Microelectronic Engineering, 120, 257-261
Open this publication in new window or tab >>Electrical properties of Ag/Ta and Ag/TaN thin-films
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2014 (English)In: Microelectronic Engineering, ISSN 0167-9317, E-ISSN 1873-5568, Vol. 120, p. 257-261Article in journal (Refereed) Published
Abstract [en]

Although wide band gap devices (WBG, e.g. GaN and SiC) are eminently suitable for high temperatures and harsh environments, these properties cannot be fully taken advantage of without an appropriate interconnect metallization. In this context, silver shows promise for interconnections at high temperatures. In this work, the thermal stability of Ag with two barrier metals – Ta and TaN – was therefore investigated. Metal stacks, consisting of 100 nm of silver on 45 nm of either Ta or TaN were sputter-deposited on the substrate. Each metal system was annealed in vacuum for one hour at temperatures up to 800 °C. Both systems showed stable performance up to 600 °C. The system with Ta as a barrier metal was found to be more stable than the TaN system. Above 700 °C, silver agglomeration led to degradation of electrical performance.

Keywords
Interconnect, Silver, Thermal stability, Ta and TaN diffusion barrier
National Category
Other Electrical Engineering, Electronic Engineering, Information Engineering
Research subject
Engineering Science with specialization in Electronics
Identifiers
urn:nbn:se:uu:diva-215831 (URN)10.1016/j.mee.2013.06.002 (DOI)000336697300045 ()
Conference
MAM 2013 - Materials for Advanced Metallization; 10-13 March 2013; Leuven, Belgium
Funder
Swedish Foundation for Strategic Research
Available from: 2014-01-17 Created: 2014-01-17 Last updated: 2017-12-06Bibliographically approved
Mardani, S., Norström, H., Olsson, J., Vallin, Ö. & Zhang, S. (2014). High-temperature behaviour of capped Ag/Ta and Ag/TaN metal stacks. In: : . Paper presented at MAM 2014 - Materials for Advanced Metallization, 2-5 March 2014, Chemnitz, Germany (pp. 137-138).
Open this publication in new window or tab >>High-temperature behaviour of capped Ag/Ta and Ag/TaN metal stacks
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2014 (English)Conference paper, Poster (with or without abstract) (Refereed)
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Research subject
Engineering Science with specialization in Electronics
Identifiers
urn:nbn:se:uu:diva-197278 (URN)
Conference
MAM 2014 - Materials for Advanced Metallization, 2-5 March 2014, Chemnitz, Germany
Funder
Swedish Foundation for Strategic Research Swedish Research Council
Available from: 2014-03-31 Created: 2013-03-21 Last updated: 2014-07-18Bibliographically approved
Mardani, S., Vallin, Ö., Wätjen, J. T., Norström, H., Olsson, J. & Zhang, S. (2014). Morphological instability of Ag films caused by phase transition in the underlying Ta barrier layer. Applied Physics Letters, 105, 071604
Open this publication in new window or tab >>Morphological instability of Ag films caused by phase transition in the underlying Ta barrier layer
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2014 (English)In: Applied Physics Letters, ISSN 0003-6951, E-ISSN 1077-3118, Vol. 105, p. 071604-Article in journal (Refereed) Published
Abstract [en]

Wide-bandgap (WBG) semiconductor technologies are maturing and may provide increased deviceperformance in many fields of applications, such as high-temperature electronics. However, thereare still issues regarding the stability and reliability of WBG devices. Of particular importance isthe high-temperature stability of interconnects for electronic systems based on WBG-semiconductors. For metallization without proper encapsulation, morphological degradation canoccur at elevated temperatures. Sandwiching Ag films between Ta and/or TaN layers in this studyis found to be electrically and morphologically stabilize the Ag metallization up to 800C, com-pared to 600C for uncapped films. However, the barrier layer plays a key role and TaN is found tobe superior to Ta, resulting in the best achieved stability, whereas the difference between Ta andTaN caps is negligible. The b-to-a phase transition in the underlying Ta barrier layer is identifiedas the major cause responsible for the morphological instability observed above 600C. It isshown that this phase transition can be avoided using a stacked Ta/TaN barrier.

Place, publisher, year, edition, pages
American Institute of Physics (AIP), 2014
National Category
Other Electrical Engineering, Electronic Engineering, Information Engineering
Research subject
Engineering Science with specialization in Electronics
Identifiers
urn:nbn:se:uu:diva-230204 (URN)10.1063/1.4893768 (DOI)000341189800016 ()
Funder
Swedish Research Council, 2010-4460Swedish Foundation for Strategic Research , RE10-0011
Available from: 2014-08-20 Created: 2014-08-20 Last updated: 2017-12-05Bibliographically approved
Li, L.-G., Lotfi, S., Vallin, Ö. & Olsson, J. (2014). Thermal characterization of polycrystalline SiC. Journal of Electronic Materials, 43(4), 1150-1153
Open this publication in new window or tab >>Thermal characterization of polycrystalline SiC
2014 (English)In: Journal of Electronic Materials, ISSN 0361-5235, E-ISSN 1543-186X, Vol. 43, no 4, p. 1150-1153Article in journal (Refereed) Published
Abstract [en]

A study is made using fabricated thermal resistors in combination with two-dimensional (2D) electrothermal simulations to determine the thermal conductivity of polycrystalline SiC, single-crystalline SiC, and Si. The results show that the poly-SiC substrate has thermal conductivity of κ poly-SiC = 2.7 W K−1 cm−1, which is significantly lower than that of single-crystalline SiC.

National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Research subject
Engineering Science with specialization in Electronics
Identifiers
urn:nbn:se:uu:diva-209759 (URN)10.1007/s11664-014-3032-6 (DOI)000334182700046 ()
Available from: 2013-10-25 Created: 2013-10-25 Last updated: 2017-12-06Bibliographically approved
Mardani, S., Liljeholm, L., Primetzhofer, D. & Vallin, Ö. (2013). Thermal stability of Ag/Ta and Ag/TaN thin-films. In: : . Paper presented at MAM 2013 - Materials for Advanced Metallization; 10-13 March 2013; Leuven, Belgium (pp. 123-124).
Open this publication in new window or tab >>Thermal stability of Ag/Ta and Ag/TaN thin-films
2013 (English)Conference paper, Poster (with or without abstract) (Refereed)
National Category
Other Electrical Engineering, Electronic Engineering, Information Engineering
Research subject
Engineering Science with specialization in Electronics
Identifiers
urn:nbn:se:uu:diva-197281 (URN)
Conference
MAM 2013 - Materials for Advanced Metallization; 10-13 March 2013; Leuven, Belgium
Funder
Swedish Research CouncilSwedish Foundation for Strategic Research
Available from: 2013-03-21 Created: 2013-03-21 Last updated: 2016-04-21Bibliographically approved
Lotfi, S., Li, L.-G., Vallin, Ö., Norström, H. & Olsson, J. (2012). Fabrication and Characterization of 150 mm Silicon-on-polycrystalline-Silicon Carbide Substrates. Journal of Electronic Materials, 41(3), 480-487
Open this publication in new window or tab >>Fabrication and Characterization of 150 mm Silicon-on-polycrystalline-Silicon Carbide Substrates
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2012 (English)In: Journal of Electronic Materials, ISSN 0361-5235, E-ISSN 1543-186X, Vol. 41, no 3, p. 480-487Article in journal (Refereed) Published
Abstract [en]

Silicon-on-insulator (SOI) substrates can reduce RF-substrate losses due to their buried oxide (BOX). On the other hand, the BOX causes problems since it acts as a thermal barrier. Oxide has low thermal conductivity and traps the heat that is generated in devices on the SOI. This paper presents a hybrid substrate which uses a thin layer of poly-crystalline silicon and poly-crystalline silicon carbide (Si-on-poly-SiC) to replace the thermally unfavorable buried oxide and the silicon substrate. 150 mm substrates were fabricated by wafer bonding and shown to be stress and strain free. Various electronic devices and test structures were processed on the hybrid substrate as well as on a low resistivity SOI reference wafer. The substrates were characterized electrically and thermally and compared to each other. Results showed that the Si-on-poly-SiC wafer had a 2.5 times lower thermal resistance and was equally or better in electrical performance compared to the SOI reference wafer.

National Category
Engineering and Technology Electrical Engineering, Electronic Engineering, Information Engineering
Research subject
Engineering Science with specialization in Electronics
Identifiers
urn:nbn:se:uu:diva-162180 (URN)10.1007/s11664-011-1827-2 (DOI)000299930100009 ()
Available from: 2011-12-12 Created: 2011-11-25 Last updated: 2017-12-08Bibliographically approved
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