Open this publication in new window or tab >>2023 (English)In: ISCA '23: Proceedings of the 50th Annual International Symposium on Computer Architecture, New York, NY: Association for Computing Machinery (ACM), 2023, article id 53Conference paper, Published paper (Refereed)
Abstract [en]
Speculative side-channel attacks have forced computer architects to rethink speculative execution. Effectively preventing microarchitectural state from leaking sensitive information will be a key requirement in future processor design.
An important limitation of many secure speculation schemes is a reduction in the available memory parallelism, as unsafe loads (depending on the particular scheme) are blocked, as they might potentially leak information. Our contribution is to show that it is possible to recover some of this lost memory parallelism, by safely predicting the addresses of these loads in a threat-model transparent way, i.e., without worsening the security guarantees of the underlying secure scheme. To demonstrate the generality of the approach, we apply it to three different secure speculation schemes: Non-speculative Data Access (NDA), Speculative Taint Tracking (STT), and Delay-on-Miss (DoM).
An address predictor is trained on non-speculative data, and can afterwards predict the addresses of unsafe slow-to-issue loads, preloading the target registers with speculative values, that can be released faster on correct predictions than starting the entire load process. This new perspective on speculative execution encompasses all loads, and gives speedups, separately from prefetching.
We call the address-predicted counterparts of loads Doppelganger Loads. They give notable performance improvements for the three secure speculation schemes we evaluate, NDA, STT, and DoM. The Doppelganger Loads reduce the geometric mean slowdown by 42%, 48%, and 30% respectively, as compared to an unsafe baseline, for a wide variety of SPEC2006 and SPEC2017 benchmarks. Furthermore, Doppelganger Loads can be efficiently implemented with only minor core modifications, reusing existing resources such as a stride prefetcher, and most importantly, requiring no changes to the memory hierarchy outside the core.
Place, publisher, year, edition, pages
New York, NY: Association for Computing Machinery (ACM), 2023
Series
Conference Proceedings Annual International Symposium on Computer Architecture, ISSN 1063-6897
Keywords
computer architecture, security, speculative side-channels, spectre
National Category
Computer Systems
Identifiers
urn:nbn:se:uu:diva-509800 (URN)10.1145/3579371.3589088 (DOI)001098723900053 ()979-8-4007-0095-8 (ISBN)
Conference
50th Annual International Symposium on Computer Architecture (ISCA), JUN 17-21, 2023, Orlando, FL, USA
Funder
Vinnova, 2021-02422Swedish Research Council, 2018-05254Swedish Research Council, 2022-04959Uppsala UniversitySwedish Foundation for Strategic Research, FUS21-0067
2023-08-222023-08-222024-02-21Bibliographically approved