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Finite Element Computations on Multicore and Graphics Processors
Uppsala universitet, Teknisk-naturvetenskapliga vetenskapsområdet, Matematisk-datavetenskapliga sektionen, Institutionen för informationsteknologi, Avdelningen för beräkningsvetenskap. Uppsala universitet, Teknisk-naturvetenskapliga vetenskapsområdet, Matematisk-datavetenskapliga sektionen, Institutionen för informationsteknologi, Tillämpad beräkningsvetenskap.
2017 (engelsk)Doktoravhandling, med artikler (Annet vitenskapelig)
Abstract [en]

In this thesis, techniques for efficient utilization of modern computer hardwarefor numerical simulation are considered. In particular, we study techniques for improving the performance of computations using the finite element method.

One of the main difficulties in finite-element computations is how to perform the assembly of the system matrix efficiently in parallel, due to its complicated memory access pattern. The challenge lies in the fact that many entries of the matrix are being updated concurrently by several parallel threads. We consider transactional memory, an exotic hardware feature for concurrent update of shared variables, and conduct benchmarks on a prototype multicore processor supporting it. Our experiments show that transactions can both simplify programming and provide good performance for concurrent updates of floating point data.

Secondly, we study a matrix-free approach to finite-element computation which avoids the matrix assembly. In addition to removing the need to store the system matrix, matrix-free methods are attractive due to their low memory footprint and therefore better match the architecture of modern processors where memory bandwidth is scarce and compute power is abundant. Motivated by this, we consider matrix-free implementations of high-order finite-element methods for execution on graphics processors, which have seen a revolutionary increase in usage for numerical computations during recent years due to their more efficient architecture. In the implementation, we exploit sum-factorization techniques for efficient evaluation of matrix-vector products, mesh coloring and atomic updates for concurrent updates, and a geometric multigrid algorithm for efficient preconditioning of iterative solvers. Our performance studies show that on the GPU, a matrix-free approach is the method of choice for elements of order two and higher, yielding both a significantly faster execution, and allowing for solution of considerably larger problems. Compared to corresponding CPU implementations executed on comparable multicore processors, the GPU implementation is about twice as fast, suggesting that graphics processors are about twice as power efficient as multicores for computations of this kind.

sted, utgiver, år, opplag, sider
Uppsala: Acta Universitatis Upsaliensis, 2017. , s. 64
Serie
Digital Comprehensive Summaries of Uppsala Dissertations from the Faculty of Science and Technology, ISSN 1651-6214 ; 1512
Emneord [en]
Finite Element Methods, GPU, Matrix-Free, Multigrid, Transactional Memory
HSV kategori
Forskningsprogram
Beräkningsvetenskap
Identifikatorer
URN: urn:nbn:se:uu:diva-320147ISBN: 978-91-554-9907-5 (tryckt)OAI: oai:DiVA.org:uu-320147DiVA, id: diva2:1088894
Disputas
2017-06-09, ITC 2446, Lägerhyddsvägen 2, Uppsala, 10:15 (engelsk)
Opponent
Veileder
Prosjekter
UPMARCTilgjengelig fra: 2017-05-16 Laget: 2017-04-17 Sist oppdatert: 2019-02-25
Delarbeid
1. Using hardware transactional memory for high-performance computing
Åpne denne publikasjonen i ny fane eller vindu >>Using hardware transactional memory for high-performance computing
Vise andre…
2011 (engelsk)Inngår i: Proc. 25th International Symposium on Parallel and Distributed Processing Workshops and PhD Forum, Piscataway, NJ: IEEE , 2011, s. 1660-1667Konferansepaper, Publicerat paper (Fagfellevurdert)
sted, utgiver, år, opplag, sider
Piscataway, NJ: IEEE, 2011
HSV kategori
Identifikatorer
urn:nbn:se:uu:diva-158551 (URN)10.1109/IPDPS.2011.322 (DOI)978-1-61284-425-1 (ISBN)
Konferanse
IPDPS Workshop on Multi-Threaded Architectures and Applications
Prosjekter
eSSENCEUPMARC
Tilgjengelig fra: 2011-09-01 Laget: 2011-09-10 Sist oppdatert: 2018-01-12bibliografisk kontrollert
2. Matrix-free finite-element operator application on graphics processing units
Åpne denne publikasjonen i ny fane eller vindu >>Matrix-free finite-element operator application on graphics processing units
2014 (engelsk)Inngår i: Euro-Par 2014: Parallel Processing Workshops, Part II, Springer, 2014, s. 450-461Konferansepaper, Publicerat paper (Fagfellevurdert)
sted, utgiver, år, opplag, sider
Springer, 2014
Serie
Lecture Notes in Computer Science ; 8806
HSV kategori
Identifikatorer
urn:nbn:se:uu:diva-238380 (URN)10.1007/978-3-319-14313-2_38 (DOI)000354785000038 ()978-3-319-14312-5 (ISBN)
Konferanse
7th Workshop on Unconventional High-Performance Computing
Prosjekter
UPMARCeSSENCE
Tilgjengelig fra: 2014-12-11 Laget: 2014-12-11 Sist oppdatert: 2018-01-11bibliografisk kontrollert
3. Matrix-free finite-element computations on graphics processors with adaptively refined unstructured meshes
Åpne denne publikasjonen i ny fane eller vindu >>Matrix-free finite-element computations on graphics processors with adaptively refined unstructured meshes
2017 (engelsk)Inngår i: Proc. 25th High Performance Computing Symposium, San Diego, CA: The Society for Modeling and Simulation International, 2017, s. 1-12Konferansepaper, Publicerat paper (Fagfellevurdert)
sted, utgiver, år, opplag, sider
San Diego, CA: The Society for Modeling and Simulation International, 2017
HSV kategori
Identifikatorer
urn:nbn:se:uu:diva-320146 (URN)978-1-5108-3822-2 (ISBN)
Konferanse
HPC 2017, April 23–26, Virginia Beach, VA
Prosjekter
UPMARC
Tilgjengelig fra: 2017-04-23 Laget: 2017-04-16 Sist oppdatert: 2018-01-13bibliografisk kontrollert
4. Multigrid for matrix-free finite element computations on graphics processors
Åpne denne publikasjonen i ny fane eller vindu >>Multigrid for matrix-free finite element computations on graphics processors
2017 (engelsk)Rapport (Annet vitenskapelig)
Serie
Technical report / Department of Information Technology, Uppsala University, ISSN 1404-3203 ; 2017-006
HSV kategori
Identifikatorer
urn:nbn:se:uu:diva-320073 (URN)
Prosjekter
UPMARCeSSENCE
Tilgjengelig fra: 2017-04-20 Laget: 2017-04-13 Sist oppdatert: 2018-01-13bibliografisk kontrollert

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