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Transcending hardware limits with software out-of-order processing
Uppsala universitet, Teknisk-naturvetenskapliga vetenskapsområdet, Matematisk-datavetenskapliga sektionen, Institutionen för informationsteknologi, Datorarkitektur och datorkommunikation.
Uppsala universitet, Teknisk-naturvetenskapliga vetenskapsområdet, Matematisk-datavetenskapliga sektionen, Institutionen för informationsteknologi, Datorarkitektur och datorkommunikation.
Uppsala universitet, Teknisk-naturvetenskapliga vetenskapsområdet, Matematisk-datavetenskapliga sektionen, Institutionen för informationsteknologi, Datorarkitektur och datorkommunikation.
Uppsala universitet, Teknisk-naturvetenskapliga vetenskapsområdet, Matematisk-datavetenskapliga sektionen, Institutionen för informationsteknologi, Datorarkitektur och datorkommunikation.ORCID-id: 0000-0002-9460-1290
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2017 (engelsk)Inngår i: IEEE Computer Architecture Letters, ISSN 1556-6056, Vol. 16, nr 2, s. 162-165Artikkel i tidsskrift (Fagfellevurdert) Published
sted, utgiver, år, opplag, sider
2017. Vol. 16, nr 2, s. 162-165
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Identifikatorer
URN: urn:nbn:se:uu:diva-334012DOI: 10.1109/LCA.2017.2672559ISI: 000418870500018OAI: oai:DiVA.org:uu-334012DiVA, id: diva2:1158495
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UPMARCTilgjengelig fra: 2017-02-22 Laget: 2017-11-20 Sist oppdatert: 2018-04-26bibliografisk kontrollert
Inngår i avhandling
1. Static instruction scheduling for high performance on energy-efficient processors
Åpne denne publikasjonen i ny fane eller vindu >>Static instruction scheduling for high performance on energy-efficient processors
2018 (engelsk)Licentiatavhandling, med artikler (Annet vitenskapelig)
Abstract [en]

New trends such as the internet-of-things and smart homes push the demands for energy-efficiency. Choosing energy-efficient hardware, however, often comes as a trade-off to high-performance. In order to strike a good balance between the two, we propose software solutions to tackle the performance bottlenecks of small and energy-efficient processors.

One of the main performance bottlenecks of processors is the discrepancy between processor and memory speed, known as the memory wall. While the processor executes instructions at a high pace, the memory is too slow to provide data in a timely manner, if data has not been cached in advance. Load instructions that require an access to memory are thereby referred to as long-latency or delinquent loads. Long latencies caused by delinquent loads are putting a strain on small processors, which have few or no resources to effectively hide the latencies. As a result, the processor may stall.

In this thesis we propose compile-time transformation techniques to mitigate the penalties of delinquent loads on small out-of-order processors, with the ultimate goal to avoid processor stalls as much as possible. Our code transformation is applicable for general-purpose code, including unknown memory dependencies, complex control flow and pointers. We further propose a software-hardware co-design that combines the code transformation technique with lightweight hardware support to hide latencies on a stall-on-use in-order processor.

sted, utgiver, år, opplag, sider
Uppsala University, 2018
Serie
IT licentiate theses / Uppsala University, Department of Information Technology, ISSN 1404-5117 ; 2018-001
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Datavetenskap
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urn:nbn:se:uu:diva-349420 (URN)
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UPMARC
Tilgjengelig fra: 2017-12-18 Laget: 2018-04-26 Sist oppdatert: 2019-02-25bibliografisk kontrollert

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