Åpne denne publikasjonen i ny fane eller vindu >>2006 (engelsk)Doktoravhandling, med artikler (Annet vitenskapelig)
Abstract [en]
Plentiful research has addressed low-complexity software-based shared-memory systems since the idea was first introduced more than two decades ago. However, software-coherent systems have not been very successful in the commercial marketplace. We believe there are two main reasons for this: lack of performance and/or lack of binary compatibility.
This thesis studies multiple aspects of how to design future binary-compatible high-performance scalable shared-memory servers while keeping the hardware complexity at a minimum. It starts with a software-based distributed shared-memory system relying on no specific hardware support and gradually moves towards architectures with simple hardware support.
The evaluation is made in a modern chip-multiprocessor environment with both high-performance compute workloads and commercial applications. It shows that implementing the coherence-violation detection in hardware while solving the interchip coherence in software allows for high-performing binary-compatible systems with very low hardware complexity. Our second-generation hardware-software hybrid performs on par with, and often better than, traditional hardware-only designs.
Based on our results, we conclude that it is not only possible to design simple systems while maintaining performance and the binary-compatibility envelope, it is often possible to get better performance than in traditional and more complex designs.
We also explore two new techniques for evaluating a new shared-memory design throughout this work: adjustable simulation fidelity and statistical multiprocessor cache modeling.
sted, utgiver, år, opplag, sider
Uppsala: Universitetsbiblioteket, 2006. s. 48
Serie
Digital Comprehensive Summaries of Uppsala Dissertations from the Faculty of Science and Technology, ISSN 1651-6214 ; 217
Emneord
shared memory, distributed shared memory, hardware-software trade-off, software coherence, coherence profiling, remote access cache, chip multiprocessor, simultaneous multi threading, simulation, workload characterization, statistical cache model
HSV kategori
Identifikatorer
urn:nbn:se:uu:diva-7135 (URN)91-554-6647-8 (ISBN)
Disputas
2006-10-13, Auditorium Minus, Museum Gustavianum, Akademigatan 3, Uppsala, 14:15
Opponent
Veileder
2006-09-212006-09-212022-03-11bibliografisk kontrollert