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Fast modeling of shared caches in multicore systems
Uppsala universitet, Teknisk-naturvetenskapliga vetenskapsområdet, Matematisk-datavetenskapliga sektionen, Institutionen för informationsteknologi, Datorteknik. (UART)
Uppsala universitet, Teknisk-naturvetenskapliga vetenskapsområdet, Matematisk-datavetenskapliga sektionen, Institutionen för informationsteknologi, Datorteknik. (UART)
Uppsala universitet, Teknisk-naturvetenskapliga vetenskapsområdet, Matematisk-datavetenskapliga sektionen, Institutionen för informationsteknologi, Datorteknik. (UART)
2011 (engelsk)Inngår i: Proc. 6th International Conference on High Performance and Embedded Architectures and Compilers, New York: ACM Press , 2011, s. 147-157Konferansepaper, Publicerat paper (Fagfellevurdert)
sted, utgiver, år, opplag, sider
New York: ACM Press , 2011. s. 147-157
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Identifikatorer
URN: urn:nbn:se:uu:diva-146757DOI: 10.1145/1944862.1944885ISBN: 978-1-4503-0241-8 (tryckt)OAI: oai:DiVA.org:uu-146757DiVA, id: diva2:398936
Prosjekter
Coder-mpUPMARCTilgjengelig fra: 2011-02-20 Laget: 2011-02-20 Sist oppdatert: 2018-01-12bibliografisk kontrollert
Inngår i avhandling
1. Profiling Methods for Memory Centric Software Performance Analysis
Åpne denne publikasjonen i ny fane eller vindu >>Profiling Methods for Memory Centric Software Performance Analysis
2012 (engelsk)Doktoravhandling, med artikler (Annet vitenskapelig)
Abstract [en]

To reduce latency and increase bandwidth to memory, modern microprocessors are often designed with deep memory hierarchies including several levels of caches. For such microprocessors, both the latency and the bandwidth to off-chip memory are typically about two orders of magnitude worse than the latency and bandwidth to the fastest on-chip cache. Consequently, the performance of many applications is largely determined by how well they utilize the caches and bandwidths in the memory hierarchy. For such applications, there are two principal approaches to improve performance: optimize the memory hierarchy and optimize the software. In both cases, it is important to both qualitatively and quantitatively understand how the software utilizes and interacts with the resources (e.g., cache and bandwidths) in the memory hierarchy.

This thesis presents several novel profiling methods for memory-centric software performance analysis. The goal of these profiling methods is to provide general, high-level, quantitative information describing how the profiled applications utilize the resources in the memory hierarchy, and thereby help software and hardware developers identify opportunities for memory related hardware and software optimizations. For such techniques to be broadly applicable the data collection should have minimal impact on the profiled application, while not being dependent on custom hardware and/or operating system extensions. Furthermore, the resulting profiling information should be accurate and easy to interpret.

While several use cases are presented, the main focus of this thesis is the design and evaluation of the core profiling methods. These core profiling methods measure and/or estimate how high-level performance metrics, such as miss-and fetch ratio; off-chip bandwidth demand; and execution rate are affected by the amount of resources the profiled applications receive. This thesis shows that such high-level profiling information can be accurately obtained with very little impact on the profiled applications and without requiring costly simulations or custom hardware support.

sted, utgiver, år, opplag, sider
Uppsala: Acta Universitatis Upsaliensis, 2012. s. 51
Serie
Digital Comprehensive Summaries of Uppsala Dissertations from the Faculty of Science and Technology, ISSN 1651-6214 ; 1000
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Forskningsprogram
Datavetenskap
Identifikatorer
urn:nbn:se:uu:diva-182594 (URN)978-91-554-8541-2 (ISBN)
Disputas
2012-12-21, Room 2446, Polacksbacken, Lägerhyddsvägen 2, Uppsala, 13:00 (engelsk)
Opponent
Veileder
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UPMARC
Tilgjengelig fra: 2012-11-29 Laget: 2012-10-11 Sist oppdatert: 2018-01-12bibliografisk kontrollert

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