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Scheduling instruction effects for a statically pipelined processor
Uppsala universitet, Teknisk-naturvetenskapliga vetenskapsområdet, Matematisk-datavetenskapliga sektionen, Institutionen för informationsteknologi, Datorarkitektur och datorkommunikation. (UART)ORCID-id: 0000-0003-4232-6976
Vise andre og tillknytning
2015 (engelsk)Inngår i: Proc. International Conference on Compilers, Architectures, and Synthesis for Embedded Systems: CASES 2015, Piscataway, NJ: IEEE Press, 2015, s. 167-176Konferansepaper, Publicerat paper (Fagfellevurdert)
Abstract [en]

Statically pipelined processors have a fully exposed datapath where all portions of the pipeline are directly controlled by effects within an instruction, which simplifies hardware and enables a new level of compiler optimizations. This paper describes an effect scheduling strategy to aggressively compact instructions, which has a critical impact on code size and performance. Unique scheduling challenges include more frequent name dependences and fewer renaming opportunities due to static pipeline (SP) registers being dedicated for specific operations. We also realized the SP in a hardware implementation language (VHDL) to evaluate the real energy bene fits. Despite the compiler challenges, we achieve performance, code size, and energy improvements compared to a conventional MIPS processor.

sted, utgiver, år, opplag, sider
Piscataway, NJ: IEEE Press, 2015. s. 167-176
Emneord [en]
compiler; architecture; static pipeline; performance; energy
HSV kategori
Identifikatorer
URN: urn:nbn:se:uu:diva-260545DOI: 10.1109/CASES.2015.7324557ISI: 000380405200021ISBN: 9781467383202 (tryckt)OAI: oai:DiVA.org:uu-260545DiVA, id: diva2:847507
Konferanse
CASES 2015, October 4–9, Amsterdam, The Netherlands
Tilgjengelig fra: 2015-10-04 Laget: 2015-08-20 Sist oppdatert: 2016-08-24bibliografisk kontrollert

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