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Analytical Processor Performance and Power Modeling Using Micro-Architecture Independent Characteristics
Univ Ghent, Dept Elect & Informat Syst, Ghent, Belgium..
Intel, Kontich, Belgium..
Univ Ghent, Dept Elect & Informat Syst, Ghent, Belgium..
Uppsala universitet, Teknisk-naturvetenskapliga vetenskapsområdet, Matematisk-datavetenskapliga sektionen, Institutionen för informationsteknologi, Datorteknik.
Vise andre og tillknytning
2016 (engelsk)Inngår i: I.E.E.E. transactions on computers (Print), ISSN 0018-9340, E-ISSN 1557-9956, Vol. 65, nr 12, s. 3537-3551Artikkel i tidsskrift (Fagfellevurdert) Published
Abstract [en]

Optimizing processors for (a) specific application(s) can substantially improve energy-efficiency. With the end of Dennard scaling, and the corresponding reduction in energy-efficiency gains from technology scaling, such approaches may become increasingly important. However, designing application-specific processors requires fast design space exploration tools to optimize for the targeted application(s). Analytical models can be a good fit for such design space exploration as they provide fast performance and power estimates and insight into the interaction between an application's characteristics and the micro-architecture of a processor. Unfortunately, prior analytical models for superscalar out-of-order processors require micro-architecture dependent inputs, such as cache miss rates, branch miss rates and memory-level parallelism. This requires profiling the applications for each cache and branch predictor configuration of interest, which is far more time-consuming than evaluating the analytical performance models. In this work we present a micro-architecture independent profiler and associated analytical models that allow us to produce performance and power estimates across a large superscalar out-of-order processor design space almost instantaneously. We show that using a micro-architecture independent profile leads to a speedup of 300x compared to detailed simulation for our evaluated design space. Over a large design space, the model has a 9.3 percent average error for performance and a 4.3 percent average error for power, compared to detailed cycle-level simulation. The model is able to accurately determine the optimal processor configuration for different applications under power or performance constraints, and provides insight into performance through cycle stacks.

sted, utgiver, år, opplag, sider
2016. Vol. 65, nr 12, s. 3537-3551
Emneord [en]
Modeling, micro-architecture, performance, power
HSV kategori
Identifikatorer
URN: urn:nbn:se:uu:diva-311173DOI: 10.1109/TC.2016.2547387ISI: 000388498600003OAI: oai:DiVA.org:uu-311173DiVA, id: diva2:1059451
Tilgjengelig fra: 2016-12-22 Laget: 2016-12-22 Sist oppdatert: 2018-01-13bibliografisk kontrollert

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