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System and method for data classification and efficient virtual cache coherence without reverse translation
Uppsala University, Disciplinary Domain of Science and Technology, Mathematics and Computer Science, Department of Information Technology, Computer Systems. (UART)
Uppsala University, Disciplinary Domain of Science and Technology, Mathematics and Computer Science, Department of Information Technology, Computer Systems. (UART)
Uppsala University, Disciplinary Domain of Science and Technology, Mathematics and Computer Science, Department of Information Technology, Computer Systems. (UART)
2013 (English)Patent (Other (popular science, discussion, etc.))
Abstract [en]

An on-chip memory hierarchy organization for a multicore processing system is disclosed. The hierarchy supports virtual- addressed private caches and a physical-addressed shared cache. The hierarchy classifies cache line data as private or shared to support a one-directional request response protocol. The classification can be determined from the generational behavior of a cache line in the private caches. Cache lines having a single generation in a private cache are Private, and cache lines having overlapping generations in two or more private caches are Shared. The Private or Shared classification is performed dynamically at run-time in hardware using a single translation lookaside buffer at the interface between the private and shared caches. The coherence protocol uses the data classification in a dynamic write policy for both shared data race free data and private data, differentiating in when data is put back to the shared cache based on the classification.

Place, publisher, year, edition, pages
2013.
National Category
Computer Systems
Identifiers
URN: urn:nbn:se:uu:diva-313334OAI: oai:DiVA.org:uu-313334DiVA: diva2:1066832
Patent
WO2013186694A2
Available from: 2017-01-19 Created: 2017-01-19 Last updated: 2017-02-13

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Ros, AlbertoKaxiras, Stefanos

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