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Clairvoyance: Look-ahead compile-time scheduling
Uppsala universitet, Teknisk-naturvetenskapliga vetenskapsområdet, Matematisk-datavetenskapliga sektionen, Institutionen för informationsteknologi, Datorarkitektur och datorkommunikation. (UART)
Uppsala universitet, Teknisk-naturvetenskapliga vetenskapsområdet, Matematisk-datavetenskapliga sektionen, Institutionen för informationsteknologi, Datorarkitektur och datorkommunikation. (UART)
Uppsala universitet, Teknisk-naturvetenskapliga vetenskapsområdet, Matematisk-datavetenskapliga sektionen, Institutionen för informationsteknologi, Datorarkitektur och datorkommunikation. (UART)ORCID-id: 0000-0002-9460-1290
Uppsala universitet, Teknisk-naturvetenskapliga vetenskapsområdet, Matematisk-datavetenskapliga sektionen, Institutionen för informationsteknologi, Datorarkitektur och datorkommunikation. (UART)ORCID-id: 0000-0003-4232-6976
Vise andre og tillknytning
2017 (engelsk)Inngår i: Proc. 15th International Symposium on Code Generation and Optimization, Piscataway, NJ: IEEE Press, 2017, s. 171-184Konferansepaper, Publicerat paper (Fagfellevurdert)
sted, utgiver, år, opplag, sider
Piscataway, NJ: IEEE Press, 2017. s. 171-184
HSV kategori
Identifikatorer
URN: urn:nbn:se:uu:diva-316480ISI: 000402548700015ISBN: 978-1-5090-4931-8 (tryckt)OAI: oai:DiVA.org:uu-316480DiVA, id: diva2:1077941
Konferanse
CGO 2017, February 4–8, Austin, TX
Prosjekter
UPMARC
Forskningsfinansiär
Swedish Research Council, 2010-4741Tilgjengelig fra: 2017-02-04 Laget: 2017-03-01 Sist oppdatert: 2020-01-17bibliografisk kontrollert
Inngår i avhandling
1. Static instruction scheduling for high performance on energy-efficient processors
Åpne denne publikasjonen i ny fane eller vindu >>Static instruction scheduling for high performance on energy-efficient processors
2018 (engelsk)Licentiatavhandling, med artikler (Annet vitenskapelig)
Abstract [en]

New trends such as the internet-of-things and smart homes push the demands for energy-efficiency. Choosing energy-efficient hardware, however, often comes as a trade-off to high-performance. In order to strike a good balance between the two, we propose software solutions to tackle the performance bottlenecks of small and energy-efficient processors.

One of the main performance bottlenecks of processors is the discrepancy between processor and memory speed, known as the memory wall. While the processor executes instructions at a high pace, the memory is too slow to provide data in a timely manner, if data has not been cached in advance. Load instructions that require an access to memory are thereby referred to as long-latency or delinquent loads. Long latencies caused by delinquent loads are putting a strain on small processors, which have few or no resources to effectively hide the latencies. As a result, the processor may stall.

In this thesis we propose compile-time transformation techniques to mitigate the penalties of delinquent loads on small out-of-order processors, with the ultimate goal to avoid processor stalls as much as possible. Our code transformation is applicable for general-purpose code, including unknown memory dependencies, complex control flow and pointers. We further propose a software-hardware co-design that combines the code transformation technique with lightweight hardware support to hide latencies on a stall-on-use in-order processor.

sted, utgiver, år, opplag, sider
Uppsala University, 2018
Serie
IT licentiate theses / Uppsala University, Department of Information Technology, ISSN 1404-5117 ; 2018-001
HSV kategori
Forskningsprogram
Datavetenskap
Identifikatorer
urn:nbn:se:uu:diva-349420 (URN)
Veileder
Prosjekter
UPMARC
Tilgjengelig fra: 2017-12-18 Laget: 2018-04-26 Sist oppdatert: 2019-02-25bibliografisk kontrollert
2. Finding and Exploiting Memory-Level-Parallelism in Constrained Speculative Architectures
Åpne denne publikasjonen i ny fane eller vindu >>Finding and Exploiting Memory-Level-Parallelism in Constrained Speculative Architectures
2020 (engelsk)Doktoravhandling, med artikler (Annet vitenskapelig)
Abstract [en]

One of the main performance bottlenecks of processors today is the discrepancy between processor and memory speed, known as the memory wall. While the processor executes instructions at a high pace, the memory is too slow to provide data in a timely manner. Load instructions that require an access to memory are referred to as long-latency or delinquent loads. To prevent the processor from stalling, independent instruction past the load may execute, including independent loads. Overlapping load operations and thus their latency is referred to as memory-level parallelism. Memory-level parallelism (MLP) can significantly improve performance. Today's out-of-order processors are therefore equipped with complex hardware that allows them to look into the future and to select independent loads that can be overlapped. However, the ability to choose future instructions and speculatively execute them in advance introduces complexity, increased power consumption and potential security risks. In this thesis we look at constrained speculative architectures that struggle to hide memory latencies as they are constrained by design, by their resources, or by security. We investigate ways for the compiler to help them in finding MLP, with the ultimate goal to avoid processor stalls as much as possible. This includes small energy-efficient processors that lack the ability to look-ahead far enough to find independent loads, but also large processors that are disallowed to speculatively execute independent loads due to enforced security measures to circumvent side-channel attacks. We identify the reason for their limitation and propose software transformations and hardware extensions to overcome their restrictions.

sted, utgiver, år, opplag, sider
Uppsala: Acta Universitatis Upsaliensis, 2020. s. 50
Serie
Digital Comprehensive Summaries of Uppsala Dissertations from the Faculty of Science and Technology, ISSN 1651-6214 ; 1897
Emneord
Memory-level-parallelism, Energy-efficiency, Performance, Compiler, Instruction Scheduling, SW/HW Co-Design
HSV kategori
Forskningsprogram
Datavetenskap
Identifikatorer
urn:nbn:se:uu:diva-402642 (URN)978-91-513-0860-9 (ISBN)
Opponent
Veileder
Tilgjengelig fra: 2020-02-19 Laget: 2020-01-17 Sist oppdatert: 2020-03-13

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