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Replacing store buffers by load buffers in TSO
Uppsala University, Disciplinary Domain of Science and Technology, Mathematics and Computer Science, Department of Information Technology, Computer Systems.ORCID iD: 0000-0001-6832-6611
Uppsala University, Disciplinary Domain of Science and Technology, Mathematics and Computer Science, Department of Information Technology, Computer Systems.ORCID iD: 0000-0001-8229-3481
Uppsala University, Disciplinary Domain of Science and Technology, Mathematics and Computer Science, Department of Information Technology, Computer Systems.ORCID iD: 0000-0003-4993-0092
2018 (English)In: Verification and Evaluation of Computer and Communication Systems, Springer, 2018, p. 22-28Conference paper, Published paper (Refereed)
Abstract [en]

We consider the weak memory model of Total Store Ordering (TSO). In the classical definition of TSO, an unbounded buffer is inserted between each process and the shared memory. The buffers contains pending store operations of the processes. We introduce a new model where we replace the store buffers by load buffers. In contrast to the classical model, the buffers now contain load operations. We show that the models have equivalent behaviors in the sense that the processes reach identical sets of states when the input program is run under the two models.

Place, publisher, year, edition, pages
Springer, 2018. p. 22-28
Series
Lecture Notes in Computer Science, ISSN 0302-9743, E-ISSN 1611-3349 ; 11181
Keywords [en]
Program verification, Weak memory models, TSO
National Category
Computer Systems
Identifiers
URN: urn:nbn:se:uu:diva-366357DOI: 10.1007/978-3-030-00359-3_2ISI: 000477758000002ISBN: 978-3-030-00358-6 (print)ISBN: 978-3-030-00359-3 (electronic)OAI: oai:DiVA.org:uu-366357DiVA, id: diva2:1264390
Conference
VECoS 2018, September 26–28, Grenoble, France
Projects
UPMARCAvailable from: 2018-08-31 Created: 2018-11-20 Last updated: 2019-09-18Bibliographically approved

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Abdulla, Parosh AzizAtig, Mohamed FaouziNgo, Tuan Phong

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