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Freeway: Maximizing MLP for Slice-Out-of-Order Execution
Norwegian Univ Sci & Technol NTNU, Trondheim, Norway.
Uppsala University, Disciplinary Domain of Science and Technology, Mathematics and Computer Science, Department of Information Technology, Computer Systems.
Uppsala University, Disciplinary Domain of Science and Technology, Mathematics and Computer Science, Department of Information Technology, Computer Systems.
2019 (English)In: 2019 25th IEEE International Symposium On High Performance Computer Architecture (HPCA), IEEE, 2019, p. 558-569Conference paper, Published paper (Refereed)
Abstract [en]

Exploiting memory level parallelism (MLP) is crucial to hide long memory and last level cache access latencies. While out-of-order (OoO) cores, and techniques building on them, are effective at exploiting MLP, they deliver poor energy efficiency due to their complex hardware and the resulting energy overheads. As energy efficiency becomes the prime design constraint, we investigate low complexity/energy mechanisms to exploit MLP. This work revisits slice-out-of-order (sOoO) cores as an energy efficient alternative to OoO cores for MLP exploitation. These cores construct slices of MLP generating instructions and execute them out-of-order with respect to the rest of instructions. However, the slices and the remaining instructions, by themselves, execute in-order. Though their energy overhead is low compared to full OoO cores, sOoO cores fall considerably behind in terms of MLP extraction. We observe that their dependence-oblivious inorder slice execution causes dependent slices to frequently block MLP generation. To boost MLP generation in sOoO cores, we introduce Freeway, a sOoO core based on a new dependence-aware slice execution policy that tracks dependent slices and keeps them out of the way of MLP extraction. The proposed core incurs minimal area and power overheads, yet approaches the MLP benefits of fully OoO cores. Our evaluation shows that Freeway outperforms the state-of-the-art sOoO core by 12% and is within 7% of the MLP limits of full OoO execution.

Place, publisher, year, edition, pages
IEEE, 2019. p. 558-569
Series
International Symposium on High-Performance Computer Architecture-Proceedings, ISSN 1530-0897
National Category
Computer Engineering
Identifiers
URN: urn:nbn:se:uu:diva-387993DOI: 10.1109/HPCA.2019.00009ISI: 000469766300044ISBN: 978-1-7281-1444-6 (electronic)OAI: oai:DiVA.org:uu-387993DiVA, id: diva2:1331974
Conference
25th IEEE International Symposium on High Performance Computer Architecture (HPCA), FEB 16-20, 2019, Washington, DC
Funder
Knut and Alice Wallenberg FoundationEU, European Research Council, 715283Available from: 2019-06-27 Created: 2019-06-27 Last updated: 2019-10-31Bibliographically approved

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Alipour, MehdiBlack-Schaffer, David

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