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FIFOrder MicroArchitecture: Ready-Aware Instruction Scheduling for OoO Processors
Uppsala universitet, Teknisk-naturvetenskapliga vetenskapsområdet, Matematisk-datavetenskapliga sektionen, Institutionen för informationsteknologi, Datorteknik. Uppsala universitet, Teknisk-naturvetenskapliga vetenskapsområdet, Matematisk-datavetenskapliga sektionen, Institutionen för informationsteknologi, Datorarkitektur och datorkommunikation.ORCID-id: 0000-0001-9842-8715
Norwegian Univ Sci & Technol, Dept Comp Sci, Trondheim, Norway.
Uppsala universitet, Teknisk-naturvetenskapliga vetenskapsområdet, Matematisk-datavetenskapliga sektionen, Institutionen för informationsteknologi, Datorteknik.ORCID-id: 0000-0001-8267-0232
Uppsala universitet, Teknisk-naturvetenskapliga vetenskapsområdet, Matematisk-datavetenskapliga sektionen, Institutionen för informationsteknologi, Datorteknik.
2019 (engelsk)Inngår i: 2019 Design, Automation & Test in Europe Conference & Exhibition (DATE), IEEE, 2019, s. 716-721Konferansepaper, Publicerat paper (Fagfellevurdert)
Abstract [en]

The number of instructions a processor's instruction queue can examine (depth) and the number it can issue together (width) determine its ability to take advantage of the ILP in an application. Unfortunately, increasing either the width or depth of the instruction queue is very costly due to the content-addressable logic needed to wakeup and select instructions out-of-order. This work makes the observation that a large number of instructions have both operands ready at dispatch, and therefore do not benefit from out-of-order scheduling. We leverage this to place such ready-at-dispatch instructions in separate, simpler, in-order FIFO queues for scheduling. With such additional queues, we can reduce the size and width of the expensive out-of-order instruction queue, without reducing the processor's overall issue width and depth. Our design, FIFOrder, is able to steer more than 60% of instructions to the cheaper FIFO queues, providing a 50% energy savings over a traditional out-of-order instruction queue design, while delivering 8% higher performance.

sted, utgiver, år, opplag, sider
IEEE, 2019. s. 716-721
Serie
Design Automation and Test in Europe Conference and Exhibition, ISSN 1530-1591
HSV kategori
Identifikatorer
URN: urn:nbn:se:uu:diva-389930DOI: 10.23919/DATE.2019.8715034ISI: 000470666100132ISBN: 978-3-9819263-2-3 (digital)OAI: oai:DiVA.org:uu-389930DiVA, id: diva2:1340024
Konferanse
Design, Automation & Test in Europe Conference & Exhibition (DATE), MAR 25-29, 2019, Florence, ITALY
Forskningsfinansiär
Knut and Alice Wallenberg FoundationTilgjengelig fra: 2019-08-01 Laget: 2019-08-01 Sist oppdatert: 2020-02-02bibliografisk kontrollert
Inngår i avhandling
1. Rethinking Dynamic Instruction Scheduling and Retirement for Efficient Microarchitectures
Åpne denne publikasjonen i ny fane eller vindu >>Rethinking Dynamic Instruction Scheduling and Retirement for Efficient Microarchitectures
2020 (engelsk)Doktoravhandling, med artikler (Annet vitenskapelig)
Abstract [en]

Out-of-order execution is one of the main micro-architectural techniques used to improve the performance of both single- and multi-threaded processors. The application of such a processor varies from mobile devices to server computers. This technique achieves higher performance by finding independent instructions and hiding execution latency and uses the cycles which otherwise would be wasted or caused a CPU stall. To accomplish this, it uses scheduling resources including the ROB, IQ, LSQ and physical registers, to store and prioritize instructions.

The pipeline of an out-of-order processor has three macro-stages: the front-end, the scheduler, and the back-end. The front-end fetches instructions, places them in the out-of-order resources, and analyzes them to prepare for their execution. The scheduler identifies which instructions are ready for execution and prioritizes them for scheduling. The back-end updates the processor state with the results of the oldest completed instructions, deallocates the resources and commits the instructions in the program order to maintain correct execution.

Since out-of-order execution needs to be able to choose any available instructions for execution, its scheduling resources must have complex circuits for identifying and prioritizing instructions, which makes them very expansive, therefore, limited. Due to their cost, the scheduling resources are constrained in size. This limited size leads to two stall points respectively at the front-end and the back-end of the pipeline. The front-end can stall due to fully allocated resources and therefore no more new instructions can be placed in the scheduler. The back-end can stall due to the unfinished execution of an instruction at the head of the ROB which prevents other resources from being deallocated, preventing new instructions from being inserted into the pipeline.

To address these two stalls, this thesis focuses on reducing the time instructions occupy the scheduling resources. Our front-end technique tackles IQ pressure while our back-end approach considers the rest of the resources. To reduce front-end stalls we reduce the pressure on the IQ for both storing (depth) and issuing (width) instructions by bypassing them to cheaper storage structures. To reduce back-end stalls, we explore how we can retire instructions earlier, and out-of-order, to reduce the pressure on the out-of-order resource.

sted, utgiver, år, opplag, sider
Uppsala: Acta Universitatis Upsaliensis, 2020. s. 76
Serie
Digital Comprehensive Summaries of Uppsala Dissertations from the Faculty of Science and Technology, ISSN 1651-6214 ; 1902
Emneord
Out-of-Order Processors, Energy-Efficient, High-Performance, Instruction Scheduling
HSV kategori
Forskningsprogram
Datavetenskap
Identifikatorer
urn:nbn:se:uu:diva-403675 (URN)978-91-513-0868-5 (ISBN)
Opponent
Veileder
Tilgjengelig fra: 2020-02-27 Laget: 2020-02-02 Sist oppdatert: 2020-05-19bibliografisk kontrollert

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