uu.seUppsala universitets publikasjoner
Endre søk
RefereraExporteraLink to record
Permanent link

Direct link
Referera
Referensformat
  • apa
  • ieee
  • modern-language-association
  • vancouver
  • Annet format
Fler format
Språk
  • de-DE
  • en-GB
  • en-US
  • fi-FI
  • nn-NO
  • nn-NB
  • sv-SE
  • Annet språk
Fler språk
Utmatningsformat
  • html
  • text
  • asciidoc
  • rtf
FIFOrder MicroArchitecture: Ready-Aware Instruction Scheduling for OoO Processors
Uppsala universitet, Teknisk-naturvetenskapliga vetenskapsområdet, Matematisk-datavetenskapliga sektionen, Institutionen för informationsteknologi, Datorteknik.ORCID-id: 0000-0001-9842-8715
Norwegian Univ Sci & Technol, Dept Comp Sci, Trondheim, Norway.
Uppsala universitet, Teknisk-naturvetenskapliga vetenskapsområdet, Matematisk-datavetenskapliga sektionen, Institutionen för informationsteknologi, Datorteknik.ORCID-id: 0000-0001-8267-0232
Uppsala universitet, Teknisk-naturvetenskapliga vetenskapsområdet, Matematisk-datavetenskapliga sektionen, Institutionen för informationsteknologi, Datorteknik.
2019 (engelsk)Inngår i: 2019 Design, Automation & Test in Europe Conference & Exhibition (DATE), IEEE, 2019, s. 716-721Konferansepaper, Publicerat paper (Fagfellevurdert)
Abstract [en]

The number of instructions a processor's instruction queue can examine (depth) and the number it can issue together (width) determine its ability to take advantage of the ILP in an application. Unfortunately, increasing either the width or depth of the instruction queue is very costly due to the content-addressable logic needed to wakeup and select instructions out-of-order. This work makes the observation that a large number of instructions have both operands ready at dispatch, and therefore do not benefit from out-of-order scheduling. We leverage this to place such ready-at-dispatch instructions in separate, simpler, in-order FIFO queues for scheduling. With such additional queues, we can reduce the size and width of the expensive out-of-order instruction queue, without reducing the processor's overall issue width and depth. Our design, FIFOrder, is able to steer more than 60% of instructions to the cheaper FIFO queues, providing a 50% energy savings over a traditional out-of-order instruction queue design, while delivering 8% higher performance.

sted, utgiver, år, opplag, sider
IEEE, 2019. s. 716-721
Serie
Design Automation and Test in Europe Conference and Exhibition, ISSN 1530-1591
HSV kategori
Identifikatorer
URN: urn:nbn:se:uu:diva-389930DOI: 10.23919/DATE.2019.8715034ISI: 000470666100132ISBN: 978-3-9819263-2-3 (digital)OAI: oai:DiVA.org:uu-389930DiVA, id: diva2:1340024
Konferanse
Design, Automation & Test in Europe Conference & Exhibition (DATE), MAR 25-29, 2019, Florence, ITALY
Forskningsfinansiär
Knut and Alice Wallenberg FoundationTilgjengelig fra: 2019-08-01 Laget: 2019-08-01 Sist oppdatert: 2019-08-01bibliografisk kontrollert

Open Access i DiVA

Fulltekst mangler i DiVA

Andre lenker

Forlagets fulltekst

Personposter BETA

Alipour, MehdiKaxiras, StefanosBlack-Schaffer, David

Søk i DiVA

Av forfatter/redaktør
Alipour, MehdiKaxiras, StefanosBlack-Schaffer, David
Av organisasjonen

Søk utenfor DiVA

GoogleGoogle Scholar

doi
isbn
urn-nbn

Altmetric

doi
isbn
urn-nbn
Totalt: 43 treff
RefereraExporteraLink to record
Permanent link

Direct link
Referera
Referensformat
  • apa
  • ieee
  • modern-language-association
  • vancouver
  • Annet format
Fler format
Språk
  • de-DE
  • en-GB
  • en-US
  • fi-FI
  • nn-NO
  • nn-NB
  • sv-SE
  • Annet språk
Fler språk
Utmatningsformat
  • html
  • text
  • asciidoc
  • rtf