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Architecturally-independent and time-based characterization of SPEC CPU 2017
Uppsala University, Disciplinary Domain of Science and Technology, Mathematics and Computer Science, Department of Information Technology, Computer Architecture and Computer Communication. Uppsala University, Disciplinary Domain of Science and Technology, Mathematics and Computer Science, Department of Information Technology, Division of Computer Systems.
Uppsala University, Disciplinary Domain of Science and Technology, Mathematics and Computer Science, Department of Information Technology, Computer Architecture and Computer Communication. Uppsala University, Disciplinary Domain of Science and Technology, Mathematics and Computer Science, Department of Information Technology, Division of Computer Systems.ORCID iD: 0000-0002-8250-8574
Uppsala University, Disciplinary Domain of Science and Technology, Mathematics and Computer Science, Department of Information Technology, Computer Architecture and Computer Communication. Uppsala University, Disciplinary Domain of Science and Technology, Mathematics and Computer Science, Department of Information Technology, Division of Computer Systems.ORCID iD: 0000-0001-5375-4058
2020 (English)In: 2020 IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS), 2020, p. 107-109Conference paper, Published paper (Refereed)
Abstract [en]

Characterizing the memory behaviour of SPEC CPU benchmarks is critical to analyze bottlenecks in the execution. Unfortunately, most prior characterizations are tied to a particular system (e.g., via performance counters, fixed configurations) and missing important time-based behaviour (e.g., average over execution). While performance counters are accurate for that particular system, the results are less accurate for different micro-architectures and configurations. Most importantly, aggregate statistics (e.g., average over full execution) miss important time-based information which reveal transient phases that have significant impact on the execution. This work focuses on micro-architecturally independent, time-based characterization and analysis of the memory system behavior of SPEC CPU 2017. By collecting micro-architecturally independent and time-based information, we provide reusable data for various memory configurations.

Place, publisher, year, edition, pages
2020. p. 107-109
Series
IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS)
National Category
Computer Systems
Identifiers
URN: urn:nbn:se:uu:diva-417174DOI: 10.1109/ISPASS48437.2020.00021ISI: 000637280800011ISBN: 978-1-7281-4798-7 (electronic)ISBN: 978-1-7281-4799-4 (print)OAI: oai:DiVA.org:uu-417174DiVA, id: diva2:1458233
Conference
2020 IEEE International Symposium on Performance Analysis of Systems and Software, Boston, August 23-25, 2020
Available from: 2020-08-14 Created: 2020-08-14 Last updated: 2024-04-02Bibliographically approved
In thesis
1. Enhancing Processor Performance: Approaches for Memory Characterization, Efficient Dynamic Instruction Prefetching, and Optimized Instruction Caching
Open this publication in new window or tab >>Enhancing Processor Performance: Approaches for Memory Characterization, Efficient Dynamic Instruction Prefetching, and Optimized Instruction Caching
2024 (English)Doctoral thesis, comprehensive summary (Other academic)
Abstract [en]

Low latency access to both data and instructions is paramount for processor performance. However, memory speed has been trailing behind the processor speed and is now a dominant bottleneck in execution. While both data and instruction misses cause performance losses, data misses can be overlapped with other useful work, but instruction misses stall the front-end of the processor leading to greater performance loss than data misses.

Memory access characterization is important for designing memory hierarchies. While many works have characterised SPEC benchmark's memory behaviour, the results have been either tied to a specific micro-architecture or ignored the time-based behaviour of the benchmarks. In this thesis, we remove a majority of the micro-architectural features to characterize the intrinsic memory behaviour of the SPEC benchmarks and use this to understand how the workloads behave with various cache sizes and prefetching. In order to simplify the analysis of complex time-based results, we propose the use of MPKI Bins which divide the execution into distinct MPKI ranges. Using MPKI bins, we demonstrate that short memory-bound phases cause a significant percentage of the overall cache misses. 

For instructions, the growing instruction footprints of server workloads are causing significant performance losses due to front-end stalls that cannot be overlapped or hidden by out-of-order execution. The second part of this thesis develops a technique to enable dedicated instruction prefetchers without the area cost of separate metadata storage structures. We propose to re-purpose the branch target buffer (BTB) to store prefetcher metadata based on the insight that benchmarks that require a dedicated instruction prefetcher can tolerate increased BTB misses. Going further, we propose L2 instruction bypassing based on the insight that decreased L2 data misses deliver more benefit then the slight instruction latency reduction of having instructions in the L2. We show that L2 instruction bypass delivers more performance than a dedicated instruction prefetcher and instruction focused replacement policies. 

Place, publisher, year, edition, pages
Uppsala: Acta Universitatis Upsaliensis, 2024. p. 54
Series
Digital Comprehensive Summaries of Uppsala Dissertations from the Faculty of Science and Technology, ISSN 1651-6214 ; 2387
Keywords
Computer Architecture, Memory Systems, Server Design, Caches
National Category
Computer Systems
Research subject
Computer Science
Identifiers
urn:nbn:se:uu:diva-525875 (URN)978-91-513-2096-0 (ISBN)
Public defence
2024-05-31, 80127, Ångströmslaboratoriet, Lägerhyddsvägen 1, Uppsala, 13:00 (English)
Opponent
Supervisors
Available from: 2024-05-06 Created: 2024-04-02 Last updated: 2024-05-06

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ISPASS Extended Abstract(216 kB)559 downloads
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Appendix(14780 kB)319 downloads
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Hassan, MuhammadPark, Chang HyunBlack-Schaffer, David

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Hassan, M., Park, C. H. & Black-Schaffer, D. (2020). Raw-Data: A Reusable Characterization Of The Memory System Behavior Of SPEC 2017 And SPEC 2006.

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