Logo: to the web site of Uppsala University

uu.sePublications from Uppsala University
Change search
CiteExportLink to record
Permanent link

Direct link
Cite
Citation style
  • apa
  • ieee
  • modern-language-association
  • vancouver
  • Other style
More styles
Language
  • de-DE
  • en-GB
  • en-US
  • fi-FI
  • nn-NO
  • nn-NB
  • sv-SE
  • Other locale
More languages
Output format
  • html
  • text
  • asciidoc
  • rtf
Early Address Prediction: Efficient Pipeline Prefetch and Reuse
Uppsala University, Disciplinary Domain of Science and Technology, Mathematics and Computer Science, Department of Information Technology, Computer Systems. 2111 NE 25th Ave, Hillsboro, OR 97124 USA..ORCID iD: 0000-0002-6259-7821
Uppsala University, Disciplinary Domain of Science and Technology, Mathematics and Computer Science, Department of Information Technology, Computer Systems. Uppsala University, Disciplinary Domain of Science and Technology, Mathematics and Computer Science, Department of Information Technology, Computer Architecture and Computer Communication. Uppsala University, Disciplinary Domain of Science and Technology, Mathematics and Computer Science, Department of Information Technology, Division of Computer Systems.ORCID iD: 0000-0001-8267-0232
Uppsala University, Disciplinary Domain of Science and Technology, Mathematics and Computer Science, Department of Information Technology, Computer Systems. Uppsala University, Disciplinary Domain of Science and Technology, Mathematics and Computer Science, Department of Information Technology, Computer Architecture and Computer Communication. (uart)ORCID iD: 0000-0001-5375-4058
2021 (English)In: ACM Transactions on Architecture and Code Optimization (TACO), ISSN 1544-3566, E-ISSN 1544-3973, Vol. 18, no 3, article id 39Article in journal (Refereed) Published
Abstract [en]

Achieving low load-to-use latency with low energy and storage overheads is critical for performance. Existing techniques either prefetch into the pipeline (via address prediction and validation) or provide data reuse in the pipeline (via register sharing or LO caches). These techniques provide a range of tradeoffs between latency, reuse, and overhead. In this work, we present a pipeline prefetching technique that achieves state-of-the-art performance and data reuse without additional data storage, data movement, or validation overheads by adding address tags to the register file. Our addition of register file tags allows us to forward (reuse) load data from the register file with no additional data movement, keep the data alive in the register file beyond the instruction's lifetime to increase temporal reuse, and coalesce prefetch requests to achieve spatial reuse. Further, we show that we can use the existing memory order violation detection hardware to validate prefetches and data forwards without additional overhead. Our design achieves the performance of existing pipeline prefetching while also forwarding 32% of the loads from the register file (compared to 15% in state-of-the-art register sharing), delivering a 16% reduction in L1 dynamic energy (1.6% total processor energy), with an area overhead of less than 0.5%.

Place, publisher, year, edition, pages
ASSOC COMPUTING MACHINERY Association for Computing Machinery (ACM), 2021. Vol. 18, no 3, article id 39
Keywords [en]
Pipeline prefetching, first level cache, energy efficient computing, address prediction, register sharing
National Category
Computer Systems
Identifiers
URN: urn:nbn:se:uu:diva-452936DOI: 10.1145/3458883ISI: 000668433900015OAI: oai:DiVA.org:uu-452936DiVA, id: diva2:1593588
Available from: 2021-09-13 Created: 2021-09-13 Last updated: 2024-01-15Bibliographically approved

Open Access in DiVA

fulltext(1555 kB)356 downloads
File information
File name FULLTEXT01.pdfFile size 1555 kBChecksum SHA-512
d7dde4cd37802c02b264b302eb27fb26d75c46a374f3f6d82468f4629099764a012494ea4e3ec1920b1e6e004fd1fd36890d49ae7b7b4fe44ff4c3474415868d
Type fulltextMimetype application/pdf

Other links

Publisher's full text

Authority records

Alves, RicardoKaxiras, StefanosBlack-Schaffer, David

Search in DiVA

By author/editor
Alves, RicardoKaxiras, StefanosBlack-Schaffer, David
By organisation
Computer SystemsComputer Architecture and Computer CommunicationDivision of Computer Systems
In the same journal
ACM Transactions on Architecture and Code Optimization (TACO)
Computer Systems

Search outside of DiVA

GoogleGoogle Scholar
Total: 359 downloads
The number of downloads is the sum of all downloads of full texts. It may include eg previous versions that are now no longer available

doi
urn-nbn

Altmetric score

doi
urn-nbn
Total: 630 hits
CiteExportLink to record
Permanent link

Direct link
Cite
Citation style
  • apa
  • ieee
  • modern-language-association
  • vancouver
  • Other style
More styles
Language
  • de-DE
  • en-GB
  • en-US
  • fi-FI
  • nn-NO
  • nn-NB
  • sv-SE
  • Other locale
More languages
Output format
  • html
  • text
  • asciidoc
  • rtf