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Exploring the Latency Sensitivity of Cache Replacement Policies
Uppsala University, Disciplinary Domain of Science and Technology, Mathematics and Computer Science, Department of Information Technology, Division of Computer Systems. Uppsala University, Disciplinary Domain of Science and Technology, Mathematics and Computer Science, Department of Information Technology, Computer Architecture and Computer Communication.ORCID iD: 0000-0002-2767-8466
Uppsala University, Disciplinary Domain of Science and Technology, Mathematics and Computer Science, Department of Information Technology, Division of Computer Systems. Uppsala University, Disciplinary Domain of Science and Technology, Mathematics and Computer Science, Department of Information Technology, Computer Architecture and Computer Communication.ORCID iD: 0000-0002-8250-8574
Uppsala University, Disciplinary Domain of Science and Technology, Mathematics and Computer Science, Department of Information Technology, Division of Computer Systems. Uppsala University, Disciplinary Domain of Science and Technology, Mathematics and Computer Science, Department of Information Technology, Computer Architecture and Computer Communication.ORCID iD: 0000-0001-5375-4058
2023 (English)In: IEEE Computer Architecture Letters, ISSN 1556-6056, Vol. 22, no 2, p. 93-96Article in journal, Letter (Refereed) Published
Abstract [en]

With DRAM latencies increasing relative to CPU speeds, the performance of caches has become more important. This has led to increasingly sophisticated replacement policies that require complex calculations to update their replacement metadata, which often require multiple cycles. To minimize the negative impact of these metadata updates, architects have focused on policies that incur as little update latency as possible through a combination of reducing the policies’ precision and using parallel hardware. In this work we investigate whether these tradeoffs to reduce cache metadata update latency are needed. Specifically, we look at the performance and energy impact of increasing the latency of cache replacement policy updates. We find that even dramatic increases in replacement policy update latency have very limited effect. This indicates that designers have far more freedom to increase policy complexity and latency than previously assumed.

Place, publisher, year, edition, pages
Institute of Electrical and Electronics Engineers (IEEE), 2023. Vol. 22, no 2, p. 93-96
Keywords [en]
Cache Replacement Policies, Computer Architecture, High-Performance Computing
National Category
Computer Sciences
Research subject
Computer Science
Identifiers
URN: urn:nbn:se:uu:diva-508114DOI: 10.1109/lca.2023.3296251ISI: 001049956900003OAI: oai:DiVA.org:uu-508114DiVA, id: diva2:1783368
Funder
Knut and Alice Wallenberg Foundation, 2015.0153EU, Horizon 2020, 715283Swedish Research Council, 2019-02429Available from: 2023-07-20 Created: 2023-07-20 Last updated: 2024-04-05Bibliographically approved

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Nematallah, AhmedPark, Chang HyunBlack-Schaffer, David

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