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Stateless model checking for POWER
Uppsala universitet, Teknisk-naturvetenskapliga vetenskapsområdet, Matematisk-datavetenskapliga sektionen, Institutionen för informationsteknologi, Datorteknik.
Uppsala universitet, Teknisk-naturvetenskapliga vetenskapsområdet, Matematisk-datavetenskapliga sektionen, Institutionen för informationsteknologi, Datorteknik.
Uppsala universitet, Teknisk-naturvetenskapliga vetenskapsområdet, Matematisk-datavetenskapliga sektionen, Institutionen för informationsteknologi, Datorteknik.
Uppsala universitet, Teknisk-naturvetenskapliga vetenskapsområdet, Matematisk-datavetenskapliga sektionen, Institutionen för informationsteknologi, Datorteknik.
2016 (engelsk)Inngår i: Computer Aided Verification: Part II, Springer, 2016, s. 134-156Konferansepaper, Publicerat paper (Fagfellevurdert)
Abstract [en]

We present the first framework for efficient application of stateless model checking (SMC) to programs running under the relaxed memory model of POWER. The framework combines several contributions. The first contribution is that we develop a scheme for systematically deriving operational execution models from existing axiomatic ones. The scheme is such that the derived execution models are well suited for efficient SMC. We apply our scheme to the axiomatic model of POWER from [8]. Our main contribution is a technique for efficient SMC, called Relaxed Stateless Model Checking (RSMC), which systematically explores the possible inequivalent executions of a program. RSMC is suitable for execution models obtained using our scheme. We prove that RSMC is sound and optimal for the POWER memory model, in the sense that each complete program behavior is explored exactly once. We show the feasibility of our technique by providing an implementation for programs written in C/pthreads.

sted, utgiver, år, opplag, sider
Springer, 2016. s. 134-156
Serie
Lecture Notes in Computer Science, ISSN 0302-9743 ; 9780
HSV kategori
Identifikatorer
URN: urn:nbn:se:uu:diva-295424DOI: 10.1007/978-3-319-41540-6_8ISI: 000387731400008ISBN: 9783319415390 (tryckt)ISBN: 9783319415406 (tryckt)OAI: oai:DiVA.org:uu-295424DiVA, id: diva2:933649
Konferanse
CAV 2016, July 17–23, Toronto, Canada
Prosjekter
UPMARCTilgjengelig fra: 2016-07-13 Laget: 2016-06-07 Sist oppdatert: 2018-01-10bibliografisk kontrollert
Inngår i avhandling
1. Verification of Software under Relaxed Memory
Åpne denne publikasjonen i ny fane eller vindu >>Verification of Software under Relaxed Memory
2016 (engelsk)Doktoravhandling, med artikler (Annet vitenskapelig)
Abstract [en]

The work covered in this thesis concerns automatic analysis of correctness of parallel programs running under relaxed memory models.

When a parallel program is compiled and executed on a modern architecture, various optimizations may cause it to behave in unexpected ways. In particular, accesses to the shared memory may appear in the execution in the opposite order to how they appear in the control flow of the original program source code. The memory model determines which memory accesses can be reordered in a program on a given system. Any memory model that allows some observable memory access reordering is called a relaxed memory model. The reorderings may cause bugs and make the production of parallel programs more difficult.

In this work, we consider three main approaches to analysis of correctness of programs running under relaxed memory models. An exact analysis for finite state programs running under the TSO memory model (Paper I). This technique is based on the well quasi ordering framework. An over-approximate analysis for integer programs running under TSO (Paper II), based on predicate abstraction combined with a buffer abstraction. Two under-approximate analysis techniques for programs running under the TSO, PSO or POWER memory models (Papers III and IV). The latter two techniques are based on stateless model checking and dynamic partial order reduction.

In addition to determining whether a program is correct under a given memory model, the problem of automatic fence synthesis is also considered. A memory fence is an instruction that can be inserted into a program in order to locally disable some memory access reorderings. The fence synthesis problem is the problem of automatically inferring a minimal set of memory fences which restores sufficient order in a given program to ensure its correctness.

sted, utgiver, år, opplag, sider
Uppsala: Acta Universitatis Upsaliensis, 2016. s. 102
Serie
Digital Comprehensive Summaries of Uppsala Dissertations from the Faculty of Science and Technology, ISSN 1651-6214 ; 1387
Emneord
verification, relaxed memory models
HSV kategori
Forskningsprogram
Datavetenskap
Identifikatorer
urn:nbn:se:uu:diva-297201 (URN)978-91-554-9616-6 (ISBN)
Eksternt samarbeid:
Disputas
2016-09-07, 2446, Polacksbacken, Lägerhyddsvägen 2, Uppsala, 13:15 (engelsk)
Opponent
Veileder
Prosjekter
UPMARC
Tilgjengelig fra: 2016-08-17 Laget: 2016-06-22 Sist oppdatert: 2018-01-10

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