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Full speed ahead: Detailed architectural simulation at near-native speed
Uppsala University, Disciplinary Domain of Science and Technology, Mathematics and Computer Science, Department of Information Technology, Computer Architecture and Computer Communication. (UART)
Uppsala University, Disciplinary Domain of Science and Technology, Mathematics and Computer Science, Department of Information Technology, Computer Architecture and Computer Communication. (UART)
Uppsala University, Disciplinary Domain of Science and Technology, Mathematics and Computer Science, Department of Information Technology, Computer Architecture and Computer Communication. (UART)
Uppsala University, Disciplinary Domain of Science and Technology, Mathematics and Computer Science, Department of Information Technology, Computer Architecture and Computer Communication. (UART)
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2015 (English)In: Proc. 18th International Symposium on Workload Characterization, IEEE Computer Society, 2015, 183-192 p.Conference paper, Published paper (Refereed)
Abstract [en]

Cycle-level microarchitectural simulation is the defacto standard to estimate performance of next-generation platforms. Unfortunately, the level of detail needed for accurate simulation requires complex, and therefore slow, simulation models that run at speeds that are thousands of times slower than native execution. With the introduction of sampled simulation, it has become possible to simulate only the key, representative portions of a workload in a reasonable amount of time and reliably estimate its overall performance. These sampling methodologies provide the ability to identify regions for detailed execution, and through microarchitectural state checkpointing, one can quickly and easily determine the performance characteristics of a workload for a variety of microarchitectural changes. While this strategy of sampling simulations to generate checkpoints performs well for static applications, more complex scenarios involving hardware-software co-design (such as co-optimizing both a Java virtual machine and the microarchitecture it is running on) cause this methodology to break down, as new microarchitectural checkpoints are needed for each memory hierarchy configuration and software version. Solutions are therefore needed to enable fast and accurate simulation that also address the needs of hardware-software co-design and exploration. In this work we present a methodology to enhance checkpoint-based sampled simulation. Our solution integrates hardware virtualization to provide near-native speed, virtualized fast-forwarding to regions of interest, and parallel detailed simulation. However, as we cannot warm the simulated caches during virtualized fast-forwarding, we develop a novel approach to estimate the error introduced by limited cache warming, through the use of optimistic and pessimistic warming simulations. Using virtualized fast-forwarding (which operates at 90% of native speed on average), we demonstrate a parallel sampling simulator that can be used to accurately estimate the IPC of standard workloads with an average error of 2.2% while still reaching an execution rate of 2.0 GIPS (63% of native) on average. Additionally, we demonstrate that our parallelization strategy scales almost linearly and simulates one core at up to 93% of its native execution rate, 19,000x faster than detailed simulation, while using 8 cores.

Place, publisher, year, edition, pages
IEEE Computer Society, 2015. 183-192 p.
National Category
Computer Engineering
Identifiers
URN: urn:nbn:se:uu:diva-303470DOI: 10.1109/IISWC.2015.29ISI: 000380538700023ISBN: 9781509000883 (print)OAI: oai:DiVA.org:uu-303470DiVA: diva2:971916
Conference
IISWC 2015, October 4–6, Atlanta, GA
Projects
UPMARCCoDeR-MP
Available from: 2015-11-02 Created: 2016-09-19 Last updated: 2016-11-11Bibliographically approved

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Sandberg, AndreasNikoleris, NikosCarlson, Trevor E.Hagersten, ErikKaxiras, StefanosBlack-Schaffer, David
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