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Parameterized verification
Uppsala University, Disciplinary Domain of Science and Technology, Mathematics and Computer Science, Department of Information Technology, Computer Systems.
Univ Genoa, DIBRIS, Genoa, Italy..
2016 (English)In: International Journal on Software Tools for Technology Transfer (STTT), ISSN 1433-2779, E-ISSN 1433-2787, Vol. 18, no 5, 469-473 p.Article in journal, Editorial material (Other academic) Published
Abstract [en]

The goal of parameterized verification is to prove the correctness of a system specification regardless of the number of its components. The problem is of interest in several different areas: verification of hardware design, multithreaded programs, distributed systems, and communication protocols. The problem is undecidable in general. Solutions for restricted classes of systems and properties have been studied in areas like theorem proving, model checking, automata and logic, process algebra, and constraint solving. In this introduction to the special issue, dedicated to a selection of works from the Parameterized Verification workshop PV '14 and PV '15, we survey some of the works developed in this research area.

Place, publisher, year, edition, pages
2016. Vol. 18, no 5, 469-473 p.
Keyword [en]
Formal verification, Program analysis, Concurrent and distributed systems
National Category
Computer Engineering
Identifiers
URN: urn:nbn:se:uu:diva-304668DOI: 10.1007/s10009-016-0424-3ISI: 000382011100001OAI: oai:DiVA.org:uu-304668DiVA: diva2:1033612
Available from: 2016-10-07 Created: 2016-10-07 Last updated: 2017-11-30Bibliographically approved

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