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Adaptive Coherence Batching for Trap-Based Memory Architectures
Uppsala University, Teknisk-naturvetenskapliga vetenskapsområdet, Mathematics and Computer Science, Department of Information Technology. Uppsala University, Teknisk-naturvetenskapliga vetenskapsområdet, Mathematics and Computer Science, Department of Information Technology. Uppsala University, Teknisk-naturvetenskapliga vetenskapsområdet, Mathematics and Computer Science, Department of Information Technology, Computer Systems. dator system. (uppsala architecture research team)
Uppsala University, Teknisk-naturvetenskapliga vetenskapsområdet, Mathematics and Computer Science, Department of Information Technology. Uppsala University, Teknisk-naturvetenskapliga vetenskapsområdet, Mathematics and Computer Science, Department of Information Technology. Uppsala University, Teknisk-naturvetenskapliga vetenskapsområdet, Mathematics and Computer Science, Department of Information Technology, Computer Systems. dator system. (uppsala architecture research team)
2005 (English)Report (Other scientific)
Abstract [en]

Both software-initiated and hardware-initiated prefetching have been used to accelerate shared-memory server performance. While software-initiated prefetching require instruction set and compiler support, hardware prefetching often require additional hardware structures or extra memory state.

The coherence batching scheme proposed in this paper keeps the system completely binary transparent and does not rely on any additional hardware. Hence, it can be implemented without additional hardware in software coherent systems and improve performance for already optimized and compiled binaries.

We have evaluated our proposals on a trap-based memory architecture where fine-grained coherence permission checks are done in hardware but the coherence protocol is run in software on the requesting processor. Functional full-system simulation shows that our software-only coherence-batch scheme is able to reduce the number of coherence misses with up to 60 percent compared to a system without coherence batching. The average miss reduction is 37 percent while the average bandwidth usage is reduced.

Place, publisher, year, edition, pages
Uppsala Universitet, dept of information technology , 2005.
Series
information Technology - Technical reports, 2005-016
National Category
Computer Engineering
Identifiers
URN: urn:nbn:se:uu:diva-78013OAI: oai:DiVA.org:uu-78013DiVA: diva2:105926
Available from: 2006-03-16 Created: 2006-03-16

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http://www.it.uu.se/research/publications/reports/2005-016/

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Zeffer, HåkanHagersten, Erik

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