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Vasa: A Simulator Infrastructure with Adjustable Fidelity
Uppsala University, Teknisk-naturvetenskapliga vetenskapsområdet, Mathematics and Computer Science, Department of Information Technology. Uppsala University, Teknisk-naturvetenskapliga vetenskapsområdet, Mathematics and Computer Science, Department of Information Technology, Computer Systems. dator system. (uppsala architecture research team)
Uppsala University, Teknisk-naturvetenskapliga vetenskapsområdet, Mathematics and Computer Science, Department of Information Technology. Uppsala University, Teknisk-naturvetenskapliga vetenskapsområdet, Mathematics and Computer Science, Department of Information Technology, Computer Systems. dator system. (uppsala architecture research team)
Uppsala University, Teknisk-naturvetenskapliga vetenskapsområdet, Mathematics and Computer Science, Department of Information Technology. Uppsala University, Teknisk-naturvetenskapliga vetenskapsområdet, Mathematics and Computer Science, Department of Information Technology, Computer Systems. dator system. (uppsala architecture research team)
Uppsala University, Teknisk-naturvetenskapliga vetenskapsområdet, Mathematics and Computer Science, Department of Information Technology. Uppsala University, Teknisk-naturvetenskapliga vetenskapsområdet, Mathematics and Computer Science, Department of Information Technology, Computer Systems. dator system. (uppsala architecture research team)
2005 (English)In: In Proceedings of the 17th IASTED International Conference on Parallel and Distributed Computing and Systems (PDCS 2005), Phoenix, Arizona, USA, November 2005., 2005Conference paper, Published paper (Refereed)
Abstract [en]

This article presents Vasa, a configurable high-performance multiprocessor simulation package for the Virtutech Simics full-system simulator. Vasa includes models of multilevel caches, store buffers, interconnects and memory controllers and can model complex out-of-order SMT/CMP processors in great detail. However, it can also be run in two less detailed simulation modes being up to 287 times faster on average. We compare the simulation results from a 16-way cache coherent multiprocessor system with four 4-way SMT/CMP processors in the three simulation modes. Our results indicate that for many architectural studies, it is justifiable to run the simulations in a faster less detailed mode as long as it is not the behavior of the processor itself or the first level caches that is being studied.

Place, publisher, year, edition, pages
2005.
National Category
Computer Engineering
Identifiers
URN: urn:nbn:se:uu:diva-78015OAI: oai:DiVA.org:uu-78015DiVA: diva2:105928
Available from: 2007-01-12 Created: 2007-01-12

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http://www.it.uu.se/research/group/uart/publications/wallin_2005_nov

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Hagersten, Erik

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