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POSTER: Efficient Self-Invalidation/Self-Downgrade for Critical Sections with Relaxed Semantics
Univ Murcia, E-30001 Murcia, Spain..
Uppsala University, Disciplinary Domain of Science and Technology, Mathematics and Computer Science, Department of Information Technology, Computer Systems.
Uppsala University, Disciplinary Domain of Science and Technology, Mathematics and Computer Science, Department of Information Technology, Computer Systems.
Uppsala University, Disciplinary Domain of Science and Technology, Mathematics and Computer Science, Department of Information Technology, Computer Architecture and Computer Communication.
2016 (English)In: 2016 INTERNATIONAL CONFERENCE ON PARALLEL ARCHITECTURE AND COMPILATION TECHNIQUES (PACT), 2016, 433-434 p.Conference paper, (Refereed)
Abstract [en]

Cache coherence protocols based on self-invalidation allow simpler hardware implementation compared to traditional write-invalidation protocols, by relying on data-race-free semantics and applying self-invalidation and self-downgrade on synchronization points. This work examines how self invalidation and self-downgrade are performed in relation to atomicity and ordering and shows that they do not need to be applied conservatively, as so far implemented. Our key observation is that, often, critical sections which are not ordered in time, are intended to provide only atomicity but not thread synchronization.

Place, publisher, year, edition, pages
2016. 433-434 p.
Keyword [en]
Cache coherence, memory consistency, self-invalidation, critical sections, atomicity
National Category
Computer Engineering
Identifiers
URN: urn:nbn:se:uu:diva-316349DOI: 10.1145/2967938.2974050ISI: 000392249100042ISBN: 978-1-4503-4121-9 (print)OAI: oai:DiVA.org:uu-316349DiVA: diva2:1080723
Conference
International Conference on Parallel Architectures and Compilation (PACT), SEP 11-15, 2016, Haifa, ISRAEL
Available from: 2017-03-10 Created: 2017-03-10 Last updated: 2017-03-10Bibliographically approved

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Leonardsson, CarlSakalis, ChristosKaxiras, Stefanos
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