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Transcending Hardware Limits with Software Out-of-order Processing
Uppsala University, Disciplinary Domain of Science and Technology, Mathematics and Computer Science, Department of Information Technology, Computer Systems.
Uppsala University, Disciplinary Domain of Science and Technology, Mathematics and Computer Science, Department of Information Technology, Computer Systems.
Uppsala University, Disciplinary Domain of Science and Technology, Mathematics and Computer Science, Department of Information Technology, Computer Systems.
Uppsala University, Disciplinary Domain of Science and Technology, Mathematics and Computer Science, Department of Information Technology.ORCID iD: 0000-0002-9460-1290
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(English)In: IEEE Computer Architecture LettersArticle in journal (Refereed) Accepted
Abstract [en]

Building high-performance, next-generation processors require novel techniques to allow improved performance given today’s power- and energy-efficiency requirements. Additionally, a widening gap between processor and memory performance makes it even more difficult to improve efficiency with conventional techniques. While out-of-order architectures attempt to hide this memory latency with dynamically reordered instructions, they lack the energy efficiency seen in in-order processors. Thus, our goal is to reorder the instruction stream to avoid stalls and improve utilization for energy efficiency and performance. To accomplish this goal, we propose an enhanced stall-on-use in-order core that improves energy efficiency (and therefore performance in these power-limited designes) through out-of-program-order execution. During long latency loads, the SWOOP (Software Out-of-Order Processing) core exposes additional memory- and instruction-level parallelism to perform useful, non-speculative work. The resulting instruction lookahead of the SWOOP core reaches beyond the conventional fixed-sized processor structures with the help of transparent hardware register contexts. Our results show that SWOOP demonstrates a 34% performance improvement on average compared with an in-order, stall-on-use core, with an energy reduction of 23%.

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Computer Systems
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URN: urn:nbn:se:uu:diva-334012DOI: 10.1109/LCA.2017.2672559OAI: oai:DiVA.org:uu-334012DiVA: diva2:1158495
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UPMARC
Available from: 2017-11-20 Created: 2017-11-20 Last updated: 2017-11-27Bibliographically approved

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Carlson, Trevor E.Tran, Kim-AnhJimborean, AlexandraKoukos, KonstantinosSjälander, MagnusKaxiras, Stefanos

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