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Power-performance tradeoffs in data center servers: DVFS, CPU pinning, horizontal, and vertical scaling
Umea Univ, Dept Comp Sci, SE-90187 Umea, Sweden..
Umea Univ, Dept Comp Sci, SE-90187 Umea, Sweden..
Uppsala University, Disciplinary Domain of Science and Technology, Mathematics and Computer Science, Department of Information Technology, Computer Systems. Natl Univ Singapore, Sch Comp, 13 Comp Dr, Singapore 117417, Singapore.
Umea Univ, Dept Comp Sci, SE-90187 Umea, Sweden..
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2018 (English)In: Future generations computer systems, ISSN 0167-739X, E-ISSN 1872-7115, Vol. 81, p. 114-128Article in journal (Refereed) Published
Abstract [en]

Dynamic Voltage and Frequency Scaling (DVFS), CPU pinning, horizontal, and vertical scaling, are four techniques that have been proposed as actuators to control the performance and energy consumption on data center servers. This work investigates the utility of these four actuators, and quantifies the power-performance tradeoffs associated with them. Using replicas of the German Wikipedia running on our local testbed, we perform a set of experiments to quantify the influence of DVFS, vertical and horizontal scaling, and CPU pinning on end-to-end response time (average and tail), throughput, and power consumption with different workloads. Results of the experiments show that DVFS rarely reduces the power consumption of underloaded servers by more than 5%, but it can be used to limit the maximal power consumption of a saturated server by up to 20% (at a cost of performance degradation). CPU pinning reduces the power consumption of underloaded server (by up to 7%) at the cost of performance degradation, which can be limited by choosing an appropriate CPU pinning scheme. Horizontal and vertical scaling improves both the average and tail response time, but the improvement is not proportional to the amount of resources added. The load balancing strategy has a big impact on the tail response time of horizontally scaled applications.

Place, publisher, year, edition, pages
ELSEVIER SCIENCE BV , 2018. Vol. 81, p. 114-128
Keywords [en]
Power-performance tradeoffs, Dynamic Voltage and Frequency Scaling (DVFS), CPU pinning, Horizontal scaling, Vertical scaling
National Category
Computer Engineering
Identifiers
URN: urn:nbn:se:uu:diva-345707DOI: 10.1016/j.future.2017.10.044ISI: 000423652200010OAI: oai:DiVA.org:uu-345707DiVA, id: diva2:1190372
Funder
Swedish Research Council, C0590801eSSENCE - An eScience CollaborationEU, FP7, Seventh Framework Programme, 610711, 610490EU, Horizon 2020, 732667Available from: 2018-03-14 Created: 2018-03-14 Last updated: 2018-03-14Bibliographically approved

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Carlson, Trevor E.

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