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Behind the Scenes: Memory Analysis of Graphical Workloads on Tile-based GPUs
Uppsala University, Disciplinary Domain of Science and Technology, Mathematics and Computer Science, Department of Information Technology, Computer Architecture and Computer Communication. Uppsala University, Disciplinary Domain of Science and Technology, Mathematics and Computer Science, Department of Information Technology, Division of Computer Systems. (UART)ORCID iD: 0000-0003-2314-7307
Uppsala University, Disciplinary Domain of Science and Technology, Mathematics and Computer Science, Department of Information Technology, Division of Computer Systems. Uppsala University, Disciplinary Domain of Science and Technology, Mathematics and Computer Science, Department of Information Technology, Computer Architecture and Computer Communication. Uppsala University, Disciplinary Domain of Science and Technology, Mathematics and Computer Science, Department of Information Technology, Computer Systems. (UART)
Department of Computer Science, National University of Singapore.
Uppsala University, Disciplinary Domain of Science and Technology, Mathematics and Computer Science, Department of Information Technology, Computer Architecture and Computer Communication. Uppsala University, Disciplinary Domain of Science and Technology, Mathematics and Computer Science, Department of Information Technology, Computer Systems. (UART)
2018 (English)In: 2018 IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS), Belfast, UK, 2018Conference paper, Published paper (Refereed)
Abstract [en]

Graphics rendering is a complex multi-step process whose data demands typically dominate memory system design in SoCs. GPUs create images by merging many simpler scenes for each frame. For performance, scenes are tiled into parallel tasks which produce different parts of the final output. This execution model results in complex memory behavior with bandwidth demands and data sharing varying over time, and which depends heavily on the structure of the application. To design systems that can efficiently accommodate and schedule these workloads we need to understand their behavior and diversity. In this work, we develop a quantitative characterization of the data demands of modern graphics rendering. Our approach uses an architecturally-independent analysis, identifying different types of data sharing present in the applications, independent of their scheduling. From this analysis, we present a limit study into the potential to improve memory system performance by tackling each type of data sharing. We see that there is the potential to reduce graphics bandwidth by 43% if we can take full advantage of data reuse between tasks and scenes within each frame. For the particularly complex benchmarks, capturing inter-task reuse alone has the potential to reduce bandwidth by 15% (up to 31%), while targeting inter-scene reuse could provide a savings of 60% (up to 75%). These insights provide us the opportunity to understand where we should focus design efforts for graphics memory systems.

Place, publisher, year, edition, pages
Belfast, UK, 2018.
Keywords [en]
task analysis, graphics workloads, rendering (computer graphics), cache, memory system, analysis, task-based programming, tiled architectures, GPUs
National Category
Computer Systems
Research subject
Computer Science
Identifiers
URN: urn:nbn:se:uu:diva-361214DOI: 10.1109/ISPASS.2018.00009ISBN: 978-1-5386-5010-3 (electronic)ISBN: 978-1-5386-5011-0 (print)OAI: oai:DiVA.org:uu-361214DiVA, id: diva2:1250103
Conference
2018 IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS), 2-4 April 2018, Belfast, UK
Projects
UPMARC
Note

UPMARC

Available from: 2018-09-21 Created: 2018-09-21 Last updated: 2018-09-24Bibliographically approved

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fulltext(4560 kB)21 downloads
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Publisher's full texthttps://ieeexplore.ieee.org/document/8366930/

Authority records BETA

Ceballos, GermánSembrant, AndreasCarlson, Trevor E.Black-Schaffer, David

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