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Chemical mechanical polishing for surface smoothing
Uppsala University, Disciplinary Domain of Science and Technology, Technology, Department of Engineering Sciences, Solid State Electronics.
Uppsala University, Disciplinary Domain of Science and Technology, Technology, Department of Engineering Sciences, Solid State Electronics.
2002 (English)In: Physica Scripta, ISSN 0031-8949, Vol. T101, 200-202 p.Article in journal (Refereed) Published
Place, publisher, year, edition, pages
2002. Vol. T101, 200-202 p.
National Category
Other Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
URN: urn:nbn:se:uu:diva-91921OAI: oai:DiVA.org:uu-91921DiVA: diva2:164802
Available from: 2004-05-14 Created: 2004-05-14 Last updated: 2012-09-26
In thesis
1. Chemical Mechanical Polishing of Silicon and Silicon Dioxide in Front End Processing
Open this publication in new window or tab >>Chemical Mechanical Polishing of Silicon and Silicon Dioxide in Front End Processing
2004 (English)Doctoral thesis, comprehensive summary (Other academic)
Abstract [en]

Chemical mechanical polishing (CMP) has been used for a long time in the manufacturing of prime silicon wafers for the IC industry. Lately, other substrates, such as silicon-on-insulator has become in use which requires a greater control of the silicon CMP process. CMP is used to planarize oxide interlevel dielectric and to remove excessive tungsten after plug filling in the Al interconnection technology. In Cu interconnection technology, the plugs and wiring are filled in one step and excessive Cu is removed by CMP. In front end processing, CMP is used to realize shallow trench isolation (STI), to planarize trench capacitors in dynamic random access memories (DRAM) and in novel gate concepts.

This thesis is focused on CMP for front end processing, which is the processing on the device level and the starting material. The effects of dopants, crystal orientation and process parameters on silicon removal rate are investigated. CMP and silicon wafer bonding is investigated. Also, plasma assisted wafer bonding to form InP MOS structures is investigated.

A complexity of using STI in bipolar and BiCMOS processes is the integration of STI with deep trench isolation (DTI). A process module to realize STI/DTI, which introduces a poly CMP step to planarize the deep trench filling, is presented.

Another investigated front end application is to remove the overgrowth in selectively epitaxially grown collector for a SiGe heterojunction bipolar transistor.

CMP is also investigated for rounding, which could be beneficial for stress reduction or to create microoptical devices, using a pad softer than pads used for planarization.

An issue in CMP for planarization is glazing of the pad, which results in a decrease in removal rate. To retain a stable removal rate, the pad needs to be conditioned. This thesis introduces a geometrically defined abrasive surface for pad conditioning.

Place, publisher, year, edition, pages
Uppsala: Acta Universitatis Upsaliensis, 2004. 65 p.
Series
Comprehensive Summaries of Uppsala Dissertations from the Faculty of Science and Technology, ISSN 1104-232X ; 991
Keyword
Electronics, chemical mechanical polishing, chemical mechanical planarization, silicon, silicon dioxide, front end, shallow trench isolation, deep trench isolation, bipolar transistor, BiCMOS, wafer bonding, Elektronik
National Category
Other Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:uu:diva-4304 (URN)91-554-5995-1 (ISBN)
Public defence
2004-06-04, Room 2001, Ångströmlaboratoriet, Lägerhyddsvägen 1, Uppsala, 09:30 (English)
Opponent
Supervisors
Available from: 2004-05-14 Created: 2004-05-14 Last updated: 2010-03-05Bibliographically approved

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Olsson, Jörgen

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