Analysis and Design of a Low-Voltage High-Frequency LDMOS Transistor
2002 (English)In: IEEE Transactions on Electron Devices, ISSN 0018-9383, Vol. 49, no 6, 976-980 p.Article in journal (Refereed) Published
For a low voltage lateral double-diffused MOS (LDMOS) transistor, the output performance has been improved in terms of fMAX. This is done by decreasing the output capacitance and thus decreasing the total output conductance. Extraction of the model parameters has been made and the most efficient parameter to improve was identified and linked to a specific part of the transistor structure. Layout changes in the n-well/p-base region were done as the result of the model analyses and finally, the modified devices were processed. Measurements on the improved devices showed results that closely, matched the expected, and fMAX was increased with 30% and only a slight decrease in f T. Finally, the capacitance reduction in the n-well/p-base junction was measured by direct. measurements
Place, publisher, year, edition, pages
2002. Vol. 49, no 6, 976-980 p.
LV HF LDMOS transistor, S-parameter, current-voltage characteristics, equivalent circuits, layout changes, microwave FET, model parameters, n-well/p-base junction, output capacitance, output performance, small-signal parameters, total output conductance
Other Electrical Engineering, Electronic Engineering, Information Engineering
IdentifiersURN: urn:nbn:se:uu:diva-93401DOI: 10.1109/TED.2002.1003715OAI: oai:DiVA.org:uu-93401DiVA: diva2:166863