uu.seUppsala University Publications
Change search
ReferencesLink to record
Permanent link

Direct link
Miss Penalty Reduction Using Bundled Capacity Prefetching in Multiprocessors
Uppsala University, Teknisk-naturvetenskapliga vetenskapsområdet, Mathematics and Computer Science, Department of Information Technology.
2003 In: Proceedings of the International Parallel and Distributed Processing SymposiumArticle in journal (Refereed) Published
Place, publisher, year, edition, pages
URN: urn:nbn:se:uu:diva-94442OAI: oai:DiVA.org:uu-94442DiVA: diva2:168285
Available from: 2006-04-28 Created: 2006-04-28Bibliographically approved
In thesis
1. Methods for Creating and Exploiting Data Locality
Open this publication in new window or tab >>Methods for Creating and Exploiting Data Locality
2006 (English)Doctoral thesis, comprehensive summary (Other academic)
Abstract [en]

The gap between processor speed and memory latency has led to the use of caches in the memory systems of modern computers. Programs must use the caches efficiently and exploit data locality for maximum performance. Multiprocessors, built from many processing units, are becoming commonplace not only in large servers but also in smaller systems such as personal computers. Multiprocessors require careful data locality optimizations since accesses from other processors can lead to invalidations and false sharing cache misses. This thesis explores hardware and software approaches for creating and exploiting temporal and spatial locality in multiprocessors.

We propose the capacity prefetching technique, which efficiently reduces the number of cache misses but avoids false sharing by distinguishing between cache lines involved in communication from non-communicating cache lines at run-time. Prefetching techniques often lead to increased coherence and data traffic. The new bundling technique avoids one of these drawbacks and reduces the coherence traffic in multiprocessor prefetchers. This is especially important in snoop-based systems where the coherence bandwidth is a scarce resource.

Most of the studies have been performed on advanced scientific algorithms. This thesis demonstrates that a cc-NUMA multiprocessor, with hardware data migration and replication optimizations, efficiently exploits the temporal locality in such codes. We further present a method of parallelizing a multigrid Gauss-Seidel partial differential equation solver, which creates temporal locality at the expense of increased communication. Our conclusion is that on modern chip multiprocessors, it is more important to optimize algorithms for data locality than to avoid communication, since communication can take place using a shared cache.

Place, publisher, year, edition, pages
Uppsala: Acta Universitatis Upsaliensis, 2006. 37 p.
Digital Comprehensive Summaries of Uppsala Dissertations from the Faculty of Science and Technology, ISSN 1651-6214 ; 176
data locality, temporal locality, spatial locality, prefetching, cache, cache behavior, cache coherence, snooping protocols, partial differential equation, shared-memory multiprocessor, chip multiprocessor, simulation
National Category
Computer Engineering
urn:nbn:se:uu:diva-6837 (URN)91-554-6555-2 (ISBN)
Public defence
2006-05-24, Room 2446, Polacksbacken, Lägerhyddsvägen 2D, Uppsala, 13:15 (English)
Available from: 2006-04-28 Created: 2006-04-28 Last updated: 2011-02-18Bibliographically approved

Open Access in DiVA

No full text

By organisation
Department of Information Technology

Search outside of DiVA

GoogleGoogle Scholar
The number of downloads is the sum of all downloads of full texts. It may include eg previous versions that are now no longer available

Total: 220 hits
ReferencesLink to record
Permanent link

Direct link