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Towards Low-Complexity Scalable Shared-Memory Architectures
Uppsala University, Disciplinary Domain of Science and Technology, Mathematics and Computer Science, Department of Information Technology, Division of Computer Systems. Uppsala University, Disciplinary Domain of Science and Technology, Mathematics and Computer Science, Department of Information Technology, Computer Systems.
2006 (English)Doctoral thesis, comprehensive summary (Other academic)
Abstract [en]

Plentiful research has addressed low-complexity software-based shared-memory systems since the idea was first introduced more than two decades ago. However, software-coherent systems have not been very successful in the commercial marketplace. We believe there are two main reasons for this: lack of performance and/or lack of binary compatibility.

This thesis studies multiple aspects of how to design future binary-compatible high-performance scalable shared-memory servers while keeping the hardware complexity at a minimum. It starts with a software-based distributed shared-memory system relying on no specific hardware support and gradually moves towards architectures with simple hardware support.

The evaluation is made in a modern chip-multiprocessor environment with both high-performance compute workloads and commercial applications. It shows that implementing the coherence-violation detection in hardware while solving the interchip coherence in software allows for high-performing binary-compatible systems with very low hardware complexity. Our second-generation hardware-software hybrid performs on par with, and often better than, traditional hardware-only designs.

Based on our results, we conclude that it is not only possible to design simple systems while maintaining performance and the binary-compatibility envelope, it is often possible to get better performance than in traditional and more complex designs.

We also explore two new techniques for evaluating a new shared-memory design throughout this work: adjustable simulation fidelity and statistical multiprocessor cache modeling.

Place, publisher, year, edition, pages
Uppsala: Universitetsbiblioteket , 2006. , p. 48
Series
Digital Comprehensive Summaries of Uppsala Dissertations from the Faculty of Science and Technology, ISSN 1651-6214 ; 217
Keywords [en]
shared memory, distributed shared memory, hardware-software trade-off, software coherence, coherence profiling, remote access cache, chip multiprocessor, simultaneous multi threading, simulation, workload characterization, statistical cache model
National Category
Computer Engineering
Identifiers
URN: urn:nbn:se:uu:diva-7135ISBN: 91-554-6647-8 (print)OAI: oai:DiVA.org:uu-7135DiVA, id: diva2:168836
Public defence
2006-10-13, Auditorium Minus, Museum Gustavianum, Akademigatan 3, Uppsala, 14:15
Opponent
Supervisors
Available from: 2006-09-21 Created: 2006-09-21 Last updated: 2018-01-13Bibliographically approved
List of papers
1. Exploiting Locality: A Flexible DSM Approach
Open this publication in new window or tab >>Exploiting Locality: A Flexible DSM Approach
2006 In: Proceedings of the 20th IEEE International Parallel and Distributed Processing Symposium, 2006Chapter in book (Other academic) Published
Identifiers
urn:nbn:se:uu:diva-94835 (URN)
Available from: 2006-09-21 Created: 2006-09-21Bibliographically approved
2. TMA: A Trap-Based Memory Architecture
Open this publication in new window or tab >>TMA: A Trap-Based Memory Architecture
2006 In: Proceedings of the 20th ACM International Conference on Supercomputing, 2006, p. 259-268Chapter in book (Other academic) Published
Identifiers
urn:nbn:se:uu:diva-94836 (URN)
Available from: 2006-09-21 Created: 2006-09-21Bibliographically approved
3. A Case For Low-Complexity Multi-CMP Architectures
Open this publication in new window or tab >>A Case For Low-Complexity Multi-CMP Architectures
Manuscript (Other academic)
Identifiers
urn:nbn:se:uu:diva-94837 (URN)
Available from: 2006-09-21 Created: 2006-09-21 Last updated: 2010-01-13Bibliographically approved
4. A Statistical Multiprocessor Cache Model
Open this publication in new window or tab >>A Statistical Multiprocessor Cache Model
2006 In: Proceedings of the 2006 IEEE International Symposium on Performance Analysis of System and Software, 2006, p. 89-99Chapter in book (Other academic) Published
Identifiers
urn:nbn:se:uu:diva-94838 (URN)
Available from: 2006-09-21 Created: 2006-09-21Bibliographically approved
5. Vasa: A Simulator Infrastructure with Adjustable Fidelity
Open this publication in new window or tab >>Vasa: A Simulator Infrastructure with Adjustable Fidelity
2005 In: Proceedings of the 17th IASTED International Conference on Parallel and Distributed Computing and Systems, 2005Chapter in book (Other academic) Published
Identifiers
urn:nbn:se:uu:diva-94839 (URN)
Available from: 2006-09-21 Created: 2006-09-21Bibliographically approved

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