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A Computational Load-Pull Method for TCAD Optimization of RF-Power Transistors in Bias-Modulation Applications
Uppsala University, Disciplinary Domain of Science and Technology, Technology, Department of Engineering Sciences, Solid State Electronics.
Uppsala University, Disciplinary Domain of Science and Technology, Technology, Department of Engineering Sciences, Solid State Electronics.
Uppsala University, Disciplinary Domain of Science and Technology, Technology, Department of Engineering Sciences, Solid State Electronics.
2008 (English)In: Proceedings of the 3rd European Microwave Integrated Circuits Conference, 2008Conference paper, Published paper (Refereed)
Abstract [en]

In this paper a method for TCAD evaluation of RF-Power transistors for high-efficiency operation using drain bias-modulation is presented. The method is based on large signal time-domain transient computational load-pull. With the method, intrinsic device parasitics and mechanisms affecting device efficiency under drain bias modulation can be investigated and optimized for the application making it very useful for RFIC design. A case study has been done on a CMOS compatible LDMOS. For verification under dynamic operation two-tone signals with varying envelope has been simulated. The results show a possible 15% increase in the efficiency of a modulated signal for the studied device at the expense of increased phase distortion observable also in the time-domain waveforms generated. Since the method is based on TCAD it is also useful in the investigation of e.g. dynamic breakdown during high envelope under bias-modulation operation.

Place, publisher, year, edition, pages
2008.
Keyword [en]
MOS integrated circuits, power transistors, radiofrequency integrated circuits, technology CAD (electronics), CMOS compatible LDMOS, RF-power transistors, RFIC design, TCAD optimization, bias-modulation applications, computational load-pull method
National Category
Engineering and Technology
Identifiers
URN: urn:nbn:se:uu:diva-97484DOI: 10.1109/EMICC.2008.4772269ISBN: 978-2-87487-007-1 (print)OAI: oai:DiVA.org:uu-97484DiVA: diva2:172454
Conference
EuMIC 27-28 Oct. 2008
Available from: 2008-09-04 Created: 2008-09-04 Last updated: 2016-04-12
In thesis
1. Design and Characterization of RF-Power LDMOS Transistors
Open this publication in new window or tab >>Design and Characterization of RF-Power LDMOS Transistors
2008 (English)Doctoral thesis, comprehensive summary (Other academic)
Abstract [en]

In mobile communication new applications like wireless internet and mobile video have increased the demand of data-rates. Therefore, new more wideband systems are being implemented. Power amplifiers in the base-stations that simultaneously handle these wideband signals for many terminals (handhelds) need to be highly linear with a considerable band-width.

In the past decade LDMOS has been the dominating technology for use in these RF-power amplifiers. In this work LDMOS transistors possible to fabricate in a normal CMOS process have been optimized and analyzed for RF-power applications. Their non-linear behavior has been explored using load-pull measurements. The mechanisms of the non-linear input capacitance have been analyzed using 2D TCAD simulations. The investigation shows that the input capacitance is a large contributor to phase distortion in the transistor.

Computational load-pull TCAD methods have been developed for analysis of RF-power devices in high-efficiency operation. Methods have been developed for class-F with harmonic loading and for bias-modulation. Load-pull measurements with drain-bias modulation in a novel measurement setup have also been conducted. The investigation shows that the combination of computational load-pull of physical transistor structures and direct measurement evaluation with modified load-pull is a viable alternative for future design of RF-power devices. Simulations and measurements on the designed LDMOS shows a 10 to 15 % increase in drain efficiency in mid-power range both in simulations and measurements. The computational load-pull method has also been used to investigate the power capability of LDMOS transistors on SOI. This study indicates that either a low-resistivity or high-resistivity substrate should be used in manufacturing of RF-power LDMOS transistors on SOI to achieve optimum efficiency. Based on a proper substrate selection these devices exhibit a 10 % higher drain-efficiency mainly due to lower dissipated power in the devices.

Place, publisher, year, edition, pages
Uppsala: Universitetsbiblioteket, 2008. 160 p.
Series
Digital Comprehensive Summaries of Uppsala Dissertations from the Faculty of Science and Technology, ISSN 1651-6214 ; 548
Keyword
Power Amplifiers, LDMOS transistors, RF-power, IMD, Technology CAD, Load-Pull
National Category
Other Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:uu:diva-9259 (URN)978-91-554-7269-6 (ISBN)
Public defence
2008-09-26, Polhemsalen, Ångströmlaboratoriet, Lägerhyddsv. 1, Uppsala, 10:15 (English)
Opponent
Supervisors
Available from: 2008-09-04 Created: 2008-09-04 Last updated: 2010-03-01Bibliographically approved

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Bengtsson, OlofVestling, LarsOlsson, Jörgen

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