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A Computational Load-Pull Method with Harmonic Loading for High-Efficiency Investigations
Uppsala University, Disciplinary Domain of Science and Technology, Technology, Department of Engineering Sciences, Solid State Electronics.
Uppsala University, Disciplinary Domain of Science and Technology, Technology, Department of Engineering Sciences, Solid State Electronics.
Uppsala University, Disciplinary Domain of Science and Technology, Technology, Department of Engineering Sciences, Solid State Electronics.
2009 (English)In: Solid-State Electronics, ISSN 0038-1101, E-ISSN 1879-2405, Vol. 53, no 1, 86-94 p.Article in journal (Refereed) Published
Abstract [en]

In this paper a method for TCAD evaluation of RF-power transistors in high-efficiency operation using harmonic loading is presented. The method is based on large signal time-domain computational load-pull. Active loads are used in the harmonic load-pull for simulation time reduction. With the method device performance under different harmonic load impedance can be investigated at an early stage in the design process. Alternative designs can be compared and the mechanisms affecting device efficiency in class-F can be studied at chip-level. For method validation, a case study is made on an LDMOS transistor. The transistor is load-pulled in class-AB and then optimized for efficiency at 2f0 and 3f0 using a novel approach with passive fundamental load and active harmonic loads. A swept simulation is conducted using passive fundamental and harmonic loads. Waveforms in compression are analyzed and the mechanisms creating the increased efficiency in class-F are identified by a comparative study to class-AB. Class-F harmonic termination is shown to give a 17% overall reduction of dissipated power and a 9% increase in output power. The expected efficiency increase is about 3–10% in the compression region depending on level of compression.

Place, publisher, year, edition, pages
2009. Vol. 53, no 1, 86-94 p.
Keyword [en]
Load-pull, RF-power, Power amplifiers, TCAD
National Category
Engineering and Technology
Identifiers
URN: urn:nbn:se:uu:diva-97485DOI: 10.1016/j.sse.2008.10.005ISI: 000262552200015OAI: oai:DiVA.org:uu-97485DiVA: diva2:172455
Available from: 2008-09-04 Created: 2008-09-04 Last updated: 2013-10-31
In thesis
1. Design and Characterization of RF-Power LDMOS Transistors
Open this publication in new window or tab >>Design and Characterization of RF-Power LDMOS Transistors
2008 (English)Doctoral thesis, comprehensive summary (Other academic)
Abstract [en]

In mobile communication new applications like wireless internet and mobile video have increased the demand of data-rates. Therefore, new more wideband systems are being implemented. Power amplifiers in the base-stations that simultaneously handle these wideband signals for many terminals (handhelds) need to be highly linear with a considerable band-width.

In the past decade LDMOS has been the dominating technology for use in these RF-power amplifiers. In this work LDMOS transistors possible to fabricate in a normal CMOS process have been optimized and analyzed for RF-power applications. Their non-linear behavior has been explored using load-pull measurements. The mechanisms of the non-linear input capacitance have been analyzed using 2D TCAD simulations. The investigation shows that the input capacitance is a large contributor to phase distortion in the transistor.

Computational load-pull TCAD methods have been developed for analysis of RF-power devices in high-efficiency operation. Methods have been developed for class-F with harmonic loading and for bias-modulation. Load-pull measurements with drain-bias modulation in a novel measurement setup have also been conducted. The investigation shows that the combination of computational load-pull of physical transistor structures and direct measurement evaluation with modified load-pull is a viable alternative for future design of RF-power devices. Simulations and measurements on the designed LDMOS shows a 10 to 15 % increase in drain efficiency in mid-power range both in simulations and measurements. The computational load-pull method has also been used to investigate the power capability of LDMOS transistors on SOI. This study indicates that either a low-resistivity or high-resistivity substrate should be used in manufacturing of RF-power LDMOS transistors on SOI to achieve optimum efficiency. Based on a proper substrate selection these devices exhibit a 10 % higher drain-efficiency mainly due to lower dissipated power in the devices.

Place, publisher, year, edition, pages
Uppsala: Universitetsbiblioteket, 2008. 160 p.
Series
Digital Comprehensive Summaries of Uppsala Dissertations from the Faculty of Science and Technology, ISSN 1651-6214 ; 548
Keyword
Power Amplifiers, LDMOS transistors, RF-power, IMD, Technology CAD, Load-Pull
National Category
Other Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:uu:diva-9259 (URN)978-91-554-7269-6 (ISBN)
Public defence
2008-09-26, Polhemsalen, Ångströmlaboratoriet, Lägerhyddsv. 1, Uppsala, 10:15 (English)
Opponent
Supervisors
Available from: 2008-09-04 Created: 2008-09-04 Last updated: 2010-03-01Bibliographically approved

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Bengtsson, OlofVestling, LarsOlsson, Jörgen

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