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Investigation of SOI-LDMOS for RF-power applications using Computational Load-Pull
Uppsala University, Disciplinary Domain of Science and Technology, Technology, Department of Engineering Sciences, Solid State Electronics.
Uppsala University, Disciplinary Domain of Science and Technology, Technology, Department of Engineering Sciences, Solid State Electronics.
Uppsala University, Disciplinary Domain of Science and Technology, Technology, Department of Engineering Sciences, Solid State Electronics.
2009 (English)In: IEEE Transactions on Electron Devices, ISSN 0018-9383, E-ISSN 1557-9646, Vol. 56, no 3, 505-511 p.Article in journal (Refereed) Published
Abstract [en]

Small-signal and computational load-pull simulations are used to investigate the effect of substrate resistivity on efficiency in high-power operation of high-frequency silicon-on-insulator-LDMOS transistors. Identical transistors are studied on substrates with different resistivities. Using computational load pull, their high-power performance is evaluated. The results are compared to previous investigations, relating the OFF-state output resistance to high-efficiency operation. From the large-signal simulation, an output circuit model based on a load-line match is extracted with parameters traceable from small-signal simulations. It is shown that, albeit high OFF-state output resistance is a good indication, it is not sufficient for high efficiency in a high-power operation. The bias and frequency dependence of the coupling through the substrate makes a more detailed ON-state analysis necessary. It is shown that very low resistivity and high-resistivity SOI substrates both result in a high efficiency at the studied frequency and bias point. It is also shown that a normally doped medium-resistivity substrate results in a significantly lower efficiency.

Place, publisher, year, edition, pages
2009. Vol. 56, no 3, 505-511 p.
Keyword [en]
LDMOS, RF power, silicon-on-insulator (SOI), technology CAD (TCAD)
National Category
Engineering and Technology
Identifiers
URN: urn:nbn:se:uu:diva-97486DOI: 10.1109/TED.2008.2011848ISI: 000264019300019OAI: oai:DiVA.org:uu-97486DiVA: diva2:172456
Available from: 2008-09-04 Created: 2008-09-04 Last updated: 2017-12-14
In thesis
1. Design and Characterization of RF-Power LDMOS Transistors
Open this publication in new window or tab >>Design and Characterization of RF-Power LDMOS Transistors
2008 (English)Doctoral thesis, comprehensive summary (Other academic)
Abstract [en]

In mobile communication new applications like wireless internet and mobile video have increased the demand of data-rates. Therefore, new more wideband systems are being implemented. Power amplifiers in the base-stations that simultaneously handle these wideband signals for many terminals (handhelds) need to be highly linear with a considerable band-width.

In the past decade LDMOS has been the dominating technology for use in these RF-power amplifiers. In this work LDMOS transistors possible to fabricate in a normal CMOS process have been optimized and analyzed for RF-power applications. Their non-linear behavior has been explored using load-pull measurements. The mechanisms of the non-linear input capacitance have been analyzed using 2D TCAD simulations. The investigation shows that the input capacitance is a large contributor to phase distortion in the transistor.

Computational load-pull TCAD methods have been developed for analysis of RF-power devices in high-efficiency operation. Methods have been developed for class-F with harmonic loading and for bias-modulation. Load-pull measurements with drain-bias modulation in a novel measurement setup have also been conducted. The investigation shows that the combination of computational load-pull of physical transistor structures and direct measurement evaluation with modified load-pull is a viable alternative for future design of RF-power devices. Simulations and measurements on the designed LDMOS shows a 10 to 15 % increase in drain efficiency in mid-power range both in simulations and measurements. The computational load-pull method has also been used to investigate the power capability of LDMOS transistors on SOI. This study indicates that either a low-resistivity or high-resistivity substrate should be used in manufacturing of RF-power LDMOS transistors on SOI to achieve optimum efficiency. Based on a proper substrate selection these devices exhibit a 10 % higher drain-efficiency mainly due to lower dissipated power in the devices.

Place, publisher, year, edition, pages
Uppsala: Universitetsbiblioteket, 2008. 160 p.
Series
Digital Comprehensive Summaries of Uppsala Dissertations from the Faculty of Science and Technology, ISSN 1651-6214 ; 548
Keyword
Power Amplifiers, LDMOS transistors, RF-power, IMD, Technology CAD, Load-Pull
National Category
Other Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:uu:diva-9259 (URN)978-91-554-7269-6 (ISBN)
Public defence
2008-09-26, Polhemsalen, Ångströmlaboratoriet, Lägerhyddsv. 1, Uppsala, 10:15 (English)
Opponent
Supervisors
Available from: 2008-09-04 Created: 2008-09-04 Last updated: 2010-03-01Bibliographically approved

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Bengtsson, OlofVestling, LarsOlsson, Jörgen

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