Investigation of SOI-LDMOS for RF-power applications using Computational Load-Pull
2009 (English)In: IEEE Transactions on Electron Devices, ISSN 0018-9383, Vol. 56, no 3, 505-511 p.Article in journal (Refereed) Published
Small-signal and computational load-pull simulations are used to investigate the effect of substrate resistivity on efficiency in high-power operation of high-frequency silicon-on-insulator-LDMOS transistors. Identical transistors are studied on substrates with different resistivities. Using computational load pull, their high-power performance is evaluated. The results are compared to previous investigations, relating the OFF-state output resistance to high-efficiency operation. From the large-signal simulation, an output circuit model based on a load-line match is extracted with parameters traceable from small-signal simulations. It is shown that, albeit high OFF-state output resistance is a good indication, it is not sufficient for high efficiency in a high-power operation. The bias and frequency dependence of the coupling through the substrate makes a more detailed ON-state analysis necessary. It is shown that very low resistivity and high-resistivity SOI substrates both result in a high efficiency at the studied frequency and bias point. It is also shown that a normally doped medium-resistivity substrate results in a significantly lower efficiency.
Place, publisher, year, edition, pages
2009. Vol. 56, no 3, 505-511 p.
LDMOS, RF power, silicon-on-insulator (SOI), technology CAD (TCAD)
Engineering and Technology
IdentifiersURN: urn:nbn:se:uu:diva-97486DOI: 10.1109/TED.2008.2011848ISI: 000264019300019OAI: oai:DiVA.org:uu-97486DiVA: diva2:172456