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Performance fluctuation of FinFETs with Schottky barrier source/drain
Uppsala University, Disciplinary Domain of Science and Technology, Technology, Department of Engineering Sciences, Solid State Electronics.
Uppsala University, Disciplinary Domain of Science and Technology, Technology, Department of Engineering Sciences, Solid State Electronics.
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2008 (English)In: IEEE Electron Device Letters, ISSN 0741-3106, E-ISSN 1558-0563, Vol. 29, no 5, 506-508 p.Article in journal (Refereed) Published
Abstract [en]

A considerable performance fluctuation of FinFETs featuring PtSi-based Schottky barrier source/drain is found. The Fin-channels measure 27-nm tall and 35-nm wide. Investigation of similarly processed transistors of broad gate-widths reveals a large variation in the position of the PtSi/Si interface with reference to the gate edge along the gate width. This variation suggests an uneven underlap between the PtSi and the gate from device to device for the FinFETs, since essentially only one silicide grain would be in contact with each Fin-channel at the PtSi/Si interface. The size of the underlap is expected to sensitively affect the performance of the FinFETs.

Place, publisher, year, edition, pages
2008. Vol. 29, no 5, 506-508 p.
Keyword [en]
FinFETs, gate underlap, MOSFETs, platinum silicide PtSi, Schottky barrier source/drain (SB-S/D), transmission electron microscopy (TEM)
National Category
Engineering and Technology
Identifiers
URN: urn:nbn:se:uu:diva-110409DOI: 10.1109/LED.2008.920284ISI: 000255317400027OAI: oai:DiVA.org:uu-110409DiVA: diva2:277295
Available from: 2009-11-17 Created: 2009-11-16 Last updated: 2017-12-12Bibliographically approved

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Zhang, ZhenLu, JunZhang, Shi-Li

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