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Fully Depleted UTB and Trigate N-Channel MOSFETs Featuring Low-Temperature PtSi Schottky-Barrier Contacts With Dopant Segregation
Uppsala University, Disciplinary Domain of Science and Technology, Technology, Department of Engineering Sciences, Applied Materials Sciences.
Uppsala University, Disciplinary Domain of Science and Technology, Technology, Department of Engineering Sciences.
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2009 (English)In: IEEE Electron Device Letters, ISSN 0741-3106, E-ISSN 1558-0563, Vol. 30, no 5, 541-543 p.Article in journal (Refereed) Published
Abstract [en]

Schottky-barrier source/drain (SB-S/D) presents a promising solution to reducing parasitic resistance for device architectures such as fully depleted UTB, trigate, or FinFET. In this letter, a low-temperature process (<= 700 degrees C) with PtSi-based S/D is examined for the fabrication of n-type UTB and trigate FETs on SOI substrate (t(si) = 30 nm). Dopant segregation with As was used to achieve the n-type behavior at implantation doses of 1 (.) 10(15) and 5. 10(15) cm(-2). Similar results were found for UTB devices with both doses, but trigate devices with the larger dose exhibited higher on currents and smaller process variation than their lower dose counterparts.

Place, publisher, year, edition, pages
2009. Vol. 30, no 5, 541-543 p.
Keyword [en]
Dopant segregation (DS), FinFET, platinum silicide PtSi, Schottky-barrier (SB)-MOSFET, trigate
National Category
Engineering and Technology
Identifiers
URN: urn:nbn:se:uu:diva-129092DOI: 10.1109/LED.2009.2015900ISI: 000265711700039OAI: oai:DiVA.org:uu-129092DiVA: diva2:337567
Available from: 2010-08-06 Created: 2010-08-05 Last updated: 2017-12-12Bibliographically approved

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Luo, JunLu, JunZhang, Shi-Li

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