uu.seUppsala University Publications
Change search
CiteExportLink to record
Permanent link

Direct link
Cite
Citation style
  • apa
  • ieee
  • modern-language-association
  • vancouver
  • Other style
More styles
Language
  • de-DE
  • en-GB
  • en-US
  • fi-FI
  • nn-NO
  • nn-NB
  • sv-SE
  • Other locale
More languages
Output format
  • html
  • text
  • asciidoc
  • rtf
Fixed-Priority Multiprocessor Scheduling with Liu & Layland's Utilization Bound
Uppsala University, Disciplinary Domain of Science and Technology, Mathematics and Computer Science, Department of Information Technology, Computer Systems. (Embedded Systems)
Uppsala University, Disciplinary Domain of Science and Technology, Mathematics and Computer Science, Department of Information Technology, Computer Systems. (Embedded Systems)
Uppsala University, Disciplinary Domain of Science and Technology, Mathematics and Computer Science, Department of Information Technology, Computer Systems. (Embedded Systems)
2010 (English)In: Proc. 16th Real-Time and Embedded Technology and Applications Symposium, Piscataway, NJ: IEEE , 2010, 165-174 p.Conference paper, Published paper (Refereed)
Place, publisher, year, edition, pages
Piscataway, NJ: IEEE , 2010. 165-174 p.
National Category
Computer Engineering Computer Science
Research subject
Computer Science with specialization in Embedded Systems
Identifiers
URN: urn:nbn:se:uu:diva-130901DOI: 10.1109/RTAS.2010.39ISBN: 978-1-4244-6690-0 (print)OAI: oai:DiVA.org:uu-130901DiVA: diva2:351992
Conference
RTAS 2010, April 12-15, Stockholm, Sweden
Projects
CoDeR-MPUPMARC
Available from: 2010-09-20 Created: 2010-09-17 Last updated: 2014-01-23
In thesis
1. New Techniques for Building Timing-Predictable Embedded Systems
Open this publication in new window or tab >>New Techniques for Building Timing-Predictable Embedded Systems
2013 (English)Doctoral thesis, comprehensive summary (Other academic)
Abstract [en]

Embedded systems are becoming ubiquitous in our daily life. Due to close interaction with physical world, embedded systems are typically subject to timing constraints. At design time, it must be ensured that the run-time behaviors of such systems satisfy the pre-specified timing constraints under any circumstance. In this thesis, we develop techniques to address the timing analysis problems brought by the increasing complexity of underlying hardware and software on different levels of abstraction in embedded systems design.

On the program level, we develop quantitative analysis techniques to predict the cache hit/miss behaviors for tight WCET estimation, and study two commonly used replacement policies, MRU and FIFO, which cannot be analyzed adequately using the state-of-the-art qualitative cache analysis method. Our quantitative approach greatly improves the precision of WCET estimation and discloses interesting predictability properties of these replacement policies, which are concealed in the qualitative analysis framework.

On the component level, we address the challenges raised by multi-core computing. Several fundamental problems in multiprocessor scheduling are investigated. In global scheduling, we propose an analysis method to rule out a great part of impossible system behaviors for better analysis precision, and establish conditions to guarantee the bounded responsiveness of computing tasks. In partitioned scheduling, we close a long standing open problem to generalize the famous Liu and Layland's utilization bound in uniprocessor real-time scheduling to multiprocessor systems. We also propose to use cache partitioning for multi-core systems to avoid contentions on shared caches, and solve the underlying schedulability analysis problem.

On the system level, we present techniques to improve the Real-Time Calculus (RTC) analysis framework in both efficiency and precision. First, we have developed Finitary Real-Time Calculus to solve the scalability problem of the original RTC due to period explosion. The key idea is to only maintain and operate on a limited prefix of each curve that is relevant to the final results during the whole analysis procedure. We further improve the analysis precision of EDF components in RTC, by precisely bounding the response time of each computation request.

Place, publisher, year, edition, pages
Uppsala: Acta Universitatis Upsaliensis, 2013. 45 p.
Series
Digital Comprehensive Summaries of Uppsala Dissertations from the Faculty of Science and Technology, ISSN 1651-6214 ; 1094
Keyword
Real-time systems, WCET analysis, cache analysis, abstract interpretation, multiprocessor scheduling, fixed-priority scheduling, EDF, multi-core processors, response time analysis, utilization bound, real-time calculus, scalability
National Category
Computer Engineering
Research subject
Computer Science with specialization in Real Time Systems
Identifiers
urn:nbn:se:uu:diva-209623 (URN)978-91-554-8797-3 (ISBN)
Public defence
2013-12-17, Room 2446, Polacksbacken, Lägerhyddsvägen 2, Uppsala, 13:15 (English)
Opponent
Supervisors
Available from: 2013-11-26 Created: 2013-10-22 Last updated: 2014-07-21

Open Access in DiVA

No full text

Other links

Publisher's full text

Authority records BETA

Guan, NanStigge, MartinYi, Wang

Search in DiVA

By author/editor
Guan, NanStigge, MartinYi, Wang
By organisation
Computer Systems
Computer EngineeringComputer Science

Search outside of DiVA

GoogleGoogle Scholar

doi
isbn
urn-nbn

Altmetric score

doi
isbn
urn-nbn
Total: 521 hits
CiteExportLink to record
Permanent link

Direct link
Cite
Citation style
  • apa
  • ieee
  • modern-language-association
  • vancouver
  • Other style
More styles
Language
  • de-DE
  • en-GB
  • en-US
  • fi-FI
  • nn-NO
  • nn-NB
  • sv-SE
  • Other locale
More languages
Output format
  • html
  • text
  • asciidoc
  • rtf