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Interval-based models for run-time DVFS orchestration in superscalar processors
Uppsala University, Disciplinary Domain of Science and Technology, Mathematics and Computer Science, Department of Information Technology, Computer Systems. (UART)
2010 (English)In: Proc. 7th International Conference on Computing Frontiers, New York: ACM Press , 2010, 287-296 p.Conference paper (Refereed)
Place, publisher, year, edition, pages
New York: ACM Press , 2010. 287-296 p.
National Category
Computer Engineering Computer Science
URN: urn:nbn:se:uu:diva-142687DOI: 10.1145/1787275.1787338ISBN: 978-1-4503-0044-5OAI: oai:DiVA.org:uu-142687DiVA: diva2:387809
Available from: 2010-05-19 Created: 2011-01-14 Last updated: 2016-09-02Bibliographically approved
In thesis
1. Improving Energy-Efficiency of Multicores using First-Order Modeling
Open this publication in new window or tab >>Improving Energy-Efficiency of Multicores using First-Order Modeling
2016 (English)Doctoral thesis, comprehensive summary (Other academic)
Abstract [en]

In the recent decades, power consumption has evolved to one of the most critical resources in a computer system. In the form of electricity bill in data centers, battery life in mobile devices, or thermal constraints in desktops and laptops, power consumption imposes several limitations in today’s processors and improving power and energy efficiency is one of the most urgent research topics of Computer Architecture.

Dynamic Voltage and Frequency Scaling (DVFS) and Cache Resizing are among the most popular energy saving techniques. Previous work, however, has focused on developing heuristics and trial-and-error methods that yield acceptable savings, but fail to provide insight and understanding of how these techniques affect power and performance of a computer system. In contrast, this Thesis proposes the use of first-order modeling to improve the energy efficiency of computer systems. A first-order model needs to be (i) accurate enough to efficiently drive DVFS and Cache Resizing decisions, and (ii) simple enough to eliminate the overhead of collecting the required inputs to the model. We show that such models can be constructed and successfully applied in modern systems.

For DVFS, we propose to scale frequency down to exploit applications’ memory slack, i.e., periods that the processor spends waiting for data to be fetched from the main memory. In such cases, the processor frequency can be scaled down to save energy without inordinate performance penalty. Our DVFS models can detect slack and predict the impact of DVFS in both power and performance with great accuracy. Cache Resizing, on the other hand, relies on the fact that many applications do not benefit from the vast amount of cache that modern processors are equipped with. In such cases, the cache can be resized to save static energy consumption at limited performance cost. Since both techniques are related with the memory behavior of applications, we propose a unified model to manage the two techniques in tandem and maximize energy efficiency through synergistic DVFS and Cache Resizing.

Finally, our experience with DVFS in real systems motivated us to contribute to the integration of DVFS into the gem5 simulator. Unlike other simulators that ignore the role of OS in DVFS, we extend the gem5 simulator by developing the hardware and software components that allow existing Linux DVFS infrastructure to be seamlessly integrated in the simulator.

Place, publisher, year, edition, pages
Uppsala: Acta Universitatis Upsaliensis, 2016. 52 p.
Digital Comprehensive Summaries of Uppsala Dissertations from the Faculty of Science and Technology, ISSN 1651-6214 ; 1404
Computer Architecture, DVFS, Cache Resizing, Interval modeling, Power modeling
National Category
Computer Science
Research subject
Computer Science
urn:nbn:se:uu:diva-300947 (URN)978-91-554-9652-4 (ISBN)
External cooperation:
Public defence
2016-09-29, ITC/2446, Lägerhyddsvägen 2, Uppsala, 13:00 (English)
Available from: 2016-09-06 Created: 2016-08-16 Last updated: 2016-09-13

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