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Modeling cache sharing on chip multiprocessor architectures
Uppsala University, Disciplinary Domain of Science and Technology, Mathematics and Computer Science, Department of Information Technology, Computer Systems. (UART)
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2006 (English)In: Proc. International Symposium on Workload Characterization: IISWC 2006, Piscataway, NJ: IEEE , 2006, 160-171 p.Conference paper, Published paper (Refereed)
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Piscataway, NJ: IEEE , 2006. 160-171 p.
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Computer Science
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URN: urn:nbn:se:uu:diva-21917DOI: 10.1109/IISWC.2006.302740ISBN: 1-4244-0508-4 (print)OAI: oai:DiVA.org:uu-21917DiVA: diva2:49690
Available from: 2007-01-08 Created: 2007-01-08 Last updated: 2010-12-19Bibliographically approved

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Hagersten, Erik

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