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Proving refinement using transduction
Uppsala University.
Uppsala University.
Uppsala University.
1999 (English)In: DISTRIBUTED COMPUTING, ISSN 0178-2770, Vol. 12, no 2-3, 129-149 p.Article in journal (Other scientific) Published
Abstract [en]

When designing distributed systems, one is faced with the problem of verifying a refinement between two specifications, given at different levels of abstraction. Suggested verification techniques in the literature include refinement mappings and various f

Place, publisher, year, edition, pages
SPRINGER VERLAG , 1999. Vol. 12, no 2-3, 129-149 p.
Keyword [en]
temporal logic; refinement; specification; verification; transduction; delayed simulation; sequential consistency; MODELING CONCURRENCY; PARTIAL ORDERS; SYSTEMS
Identifiers
URN: urn:nbn:se:uu:diva-27335OAI: oai:DiVA.org:uu-27335DiVA: diva2:55230
Note
Addresses: Jonsson B, Univ Uppsala, Dept Comp Syst, POB 325, S-75105 Uppsala, Sweden. Univ Uppsala, Dept Comp Syst, S-75105 Uppsala, Sweden. Weizmann Inst Sci, Dept Appl Math & Comp Sci, IL-76100 Rehovot, Israel. Tech Univ Denmark, Dept Comp Sci, DK-2800Available from: 2008-10-17 Created: 2008-10-17 Last updated: 2011-01-14

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CiteExportLink to record
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