uu.seUppsala University Publications
Change search
CiteExportLink to record
Permanent link

Direct link
Cite
Citation style
  • apa
  • ieee
  • modern-language-association
  • vancouver
  • Other style
More styles
Language
  • de-DE
  • en-GB
  • en-US
  • fi-FI
  • nn-NO
  • nn-NB
  • sv-SE
  • Other locale
More languages
Output format
  • html
  • text
  • asciidoc
  • rtf
Timed Model Checking with Abstractions: Towards Worst-Case Response Time Analysis in Resource-Sharing Manycore Systems
ETH Zurich, Department of Information Technology and Electrical Engineering. (Computer Engineering and Networks Laboratory)
Uppsala University, Disciplinary Domain of Science and Technology, Mathematics and Computer Science, Department of Information Technology, Computer Systems. (Embedded Real-Time Systems)
ETH Zurich, Department of Information Technology and Electrical Engineering. (Computer Engineering and Networks Laboratory)
ETH Zurich, Department of Information Technology and Electrical Engineering. (Computer Engineering and Networks Laboratory)
2012 (English)In: Proc. International Conference on Embedded Software (EMSOFT), ACM Press, 2012, 63-72 p.Conference paper, Published paper (Refereed)
Abstract [en]

Multicore architectures are increasingly used nowadays in embedded real-time systems. Parallel execution of tasks feigns the possibility of a massive increase in performance. However, this is usually not achieved because of contention on shared resources. Concurrently executing tasks mutually block their accesses to the shared resource, causing non-deterministic delays. Timing analysis of tasks in such systems is then far from trivial. Recently, several analytic methods have been proposed for this purpose, however, they cannot model complex arbitration schemes such as FlexRay which is a common bus arbitration protocol in the automotive industry. This paper considers real-time tasks composed of superblocks, i. e., sequences of computation and re- source accessing phases. Resource accesses such as accesses to memories and caches are synchronous, i. e., they cause execution on the processing core to stall until the access is served. For such systems, the paper presents a state-based modeling and analysis approach based on Timed Automata which can model accurately arbitration schemes of any complexity. Based on it, we compute safe bounds on the worst-case response times of tasks. The scalability of the approach is increased significantly by abstracting several cores and their tasks with one arrival curve, which represents their resource accesses and computation times. This curve is then incorporated into the Timed Automata model of the system. The accuracy and scalability of the approach are evaluated with a real-world application from the automotive industry and benchmark applications.

Place, publisher, year, edition, pages
ACM Press, 2012. 63-72 p.
Keyword [en]
Timed Automata, Real Time Calculus, Real-time Performance Analysis
National Category
Embedded Systems
Identifiers
URN: urn:nbn:se:uu:diva-183818OAI: oai:DiVA.org:uu-183818DiVA: diva2:564512
Conference
International Conference on Embedded Software (EMSOFT)
Projects
CERTAINTYUPPMARC
Funder
EU, FP7, Seventh Framework Programme
Available from: 2012-11-01 Created: 2012-11-01 Last updated: 2017-02-02

Open Access in DiVA

No full text

Authority records BETA

Lampka, Kai

Search in DiVA

By author/editor
Lampka, Kai
By organisation
Computer Systems
Embedded Systems

Search outside of DiVA

GoogleGoogle Scholar

urn-nbn

Altmetric score

urn-nbn
Total: 475 hits
CiteExportLink to record
Permanent link

Direct link
Cite
Citation style
  • apa
  • ieee
  • modern-language-association
  • vancouver
  • Other style
More styles
Language
  • de-DE
  • en-GB
  • en-US
  • fi-FI
  • nn-NO
  • nn-NB
  • sv-SE
  • Other locale
More languages
Output format
  • html
  • text
  • asciidoc
  • rtf