Efficient, snoopless, System-on-Chip coherence
2012 (English)In: SOC Conference (SOCC), 2012 IEEE International, 2012, 230-235 p.Conference paper (Refereed)
Coherence in a System-on-Chip (SoC) introduces complexity and overhead (snooping caches/directory, state bits, invalidations, etc.) in exchange for a clean and uniform shared memory model. As it is typical today, a SoC comprises a variety of cores with local caches, accelerators with local memories, and some form of shared last-level cache (LLC), all interconnected with shared buses. We propose a very simple coherence protocol, fit for this environment, that eliminates L1 snooping and its associated complexity and costs (power). In essence, we remove all coherence decisions from local caches by simply determining at the LLC whether data are private or shared. This makes a write-through policy a practical and effective alternative to maintain coherence. In the local caches, we dynamically select between writeback for private data, or write-through for shared data. Self-invalidation of the shared data on synchronization points eliminates the need to snoop, with just a data-race-free guarantee from software. Our evaluation shows that this simple protocol outperforms a traditional snooping protocol while at the same time significantly reducing L1, shared cache, and bus energy consumption.
Place, publisher, year, edition, pages
2012. 230-235 p.
, International System on Chip Conference, ISSN 2164-1676
Engineering and Technology
IdentifiersURN: urn:nbn:se:uu:diva-195463DOI: 10.1109/SOCC.2012.6398353ISBN: 9781467312950OAI: oai:DiVA.org:uu-195463DiVA: diva2:607992
25th IEEE International System-on-Chip Conference, SOCC 2012, 12 September 2012 through 14 September 2012, Niagara Falls, NY