VHDL implementation of feature-extraction algorithm for the PANDA electromagnetic calorimeter
2012 (English)In: Nuclear Instruments and Methods in Physics Research Section A: Accelerators, Spectrometers, Detectors and Associated Equipment, ISSN 0168-9002, Vol. 664, no 1, 22-28 p.Article in journal (Refereed) Published
A simple, efficient, and robust feature-extraction algorithm, developed for the digital front-end electronics of the electromagnetic calorimeter of the PANDA spectrometer at FAIR, Darmstadt, is implemented in VHDL for a commercial 16 bit 100 MHz sampling ADC. The source-code is available as an open-source project and is adaptable for other projects and sampling ADCs. Best performance with different types of signal sources can be achieved through flexible parameter selection. The on-line data-processing in FPGA enables to construct an almost dead-time free data acquisition system which is successfully evaluated as a first step towards building a complete trigger-less readout chain. Prototype setups are studied to determine the dead-time of the implemented algorithm, the rate of false triggering, timing performance, and event correlations.
Place, publisher, year, edition, pages
Elsevier, 2012. Vol. 664, no 1, 22-28 p.
Electromagnetic calorimeter, Sampling ADC readout, Digital filtering, Feature extraction, Trigger-less readout chain
Research subject Nuclear Physics
IdentifiersURN: urn:nbn:se:uu:diva-196992DOI: 10.1016/j.nima.2011.10.016OAI: oai:DiVA.org:uu-196992DiVA: diva2:611453