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FIFO Cache Analysis for WCET Estimation: A Quantitative Approach
Uppsala University, Disciplinary Domain of Science and Technology, Mathematics and Computer Science, Department of Information Technology.
2013 (English)Independent thesis Advanced level (degree of Master (Two Years)), 20 credits / 30 HE creditsStudent thesis
Abstract [en]

Although most previous work in cache analysis for WCET estimation assumes the LRU (Latest Recently Used) replacement policy, in practice more processors usesimpler non-LRU policies for lower cost, power consumption and thermal output. This paper focuses on the analysis of FIFO (First In First Out), one of the most widely used cache replacement policies. Previous analysis techniques for FIFO caches are based on the same framework as for LRU caches using qualitative always-hit/always-miss classifications. This approach, though it works well for LRU caches, is not suitable to analyze FIFO and usually leads to poor WCET estimation quality. In this paper, we propose a quantitative approach for FIFO cache analysis. Roughly speaking, the proposed quantitative analysis derives an upper bound on the "miss ratio" of an instruction (set), which can better capture the FIFO cache behavior and support more accurate WCET estimations. Experiments with benchmarks show that our proposed quantitative FIFO analysis can drastically improve the WCET estimation accuracy over previous techniques (the average overestimation ratio isreduced from around 178% to 6.5% under typical setting).

Place, publisher, year, edition, pages
2013.
Series
IT, 13 044
National Category
Engineering and Technology
Identifiers
URN: urn:nbn:se:uu:diva-202148OAI: oai:DiVA.org:uu-202148DiVA: diva2:631062
Educational program
Masters Programme in Embedded Systems
Uppsok
Technology
Supervisors
Examiners
Available from: 2013-06-20 Created: 2013-06-20 Last updated: 2013-12-03Bibliographically approved

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CiteExportLink to record
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Citation style
  • apa
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