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Supporting timing analysis by automatic bounding of loop iterations
Uppsala University, Teknisk-naturvetenskapliga vetenskapsområdet, Mathematics and Computer Science, Department of Information Technology.
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2000 (English)In: REAL-TIME SYSTEMS, ISSN 0922-6443, Vol. 18, no 2-3, 129-156 p.Article in journal (Refereed) Published
Abstract [en]

Static timing analyzers, which are used to analyze real-time systems, need to know the minimum and maximum number of iterations associated with each loop in a real-time program so accurate timing predictions can be obtained. This paper describes three com

Place, publisher, year, edition, pages
KLUWER ACADEMIC PUBL , 2000. Vol. 18, no 2-3, 129-156 p.
Keyword [en]
hard real-time systems; worst-case execution time; static analysis; REAL-TIME SYSTEMS
Identifiers
URN: urn:nbn:se:uu:diva-36506OAI: oai:DiVA.org:uu-36506DiVA: diva2:64405
Note
Addresses: Healy C, Florida State Univ, Dept Comp Sci, Tallahassee, FL 32306 USA. Florida State Univ, Dept Comp Sci, Tallahassee, FL 32306 USA. Univ Uppsala, Dept Comp Syst, S-75105 Uppsala, Sweden. Silicon Spice, Mt View, CA USA.Available from: 2008-10-17 Created: 2008-10-17 Last updated: 2011-01-14

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