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A New Perspective for Efficient Virtual-Cache Coherence
Uppsala University, Disciplinary Domain of Science and Technology, Mathematics and Computer Science, Department of Information Technology, Computer Systems. (UART)
2013 (English)In: Proceedings of the 40th Annual International Symposium on Computer Architecture, 2013, 535-546 p.Conference paper, Published paper (Refereed)
Abstract [en]

Coherent shared virtual memory (cSVM) is highly coveted for heterogeneous architectures as it will simplify program- ming across different cores and manycore accelerators. In this context, virtual L1 caches can be used to great advan- tage, e.g., saving energy consumption by eliminating address translation for hits. Unfortunately, multicore virtual-cache coherence is complex and costly because it requires reverse translation for any coherence request directed towards a vir- tual L1. The reason is the ambiguity of the virtual address due to the possibility of synonyms. In this paper, we take a radically different approach than all prior work which is focused on reverse translation. We examine the problem from the perspective of the coherence protocol. We show that if a coherence protocol adheres to certain conditions, it operates effortlessly with virtual caches, without requir- ing reverse translations even in the presence of synonyms. We show that these conditions hold in a new class of simple and efficient request-response protocols that use both self- invalidation and self-downgrade.This results in a new solu- tion for virtual-cache coherence, significantly less complex and more efficient than prior proposals. We study design choices for TLB placement under our proposal and compare them against those under a directory-MESI protocol. Our approach allows for choices that are particularly effective as for example combining all per-core TLBs in a single logical TLB in front of the last level cache. Significant area, energy, and performance benefits ensue as a result of simplifying the entire multicore memory organization. 

Place, publisher, year, edition, pages
2013. 535-546 p.
National Category
Computer Systems
Identifiers
URN: urn:nbn:se:uu:diva-208805DOI: 10.1145/2485922.2485968ISBN: 978-1-4503-2079-5 (print)OAI: oai:DiVA.org:uu-208805DiVA: diva2:654632
Conference
The 40th International Symposium on Computer Architecture (ISCA), 23-27th June, 2013, Tel Aviv, Israel
Projects
UPMARCLPGPU
Available from: 2013-10-08 Created: 2013-10-08 Last updated: 2014-06-18Bibliographically approved

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Kaxiras, Stefanos

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