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A +32.8 dBm LDMOS power amplifier for WLAN in 65 nm CMOS technology
Linköping University. (Electronic Devices)
Ferdinand-Braun Institut. (Leibniz-Institut fuer Hoechstfrequenztechnik)
Uppsala University, Disciplinary Domain of Science and Technology, Technology, Department of Engineering Sciences, Solid State Electronics.
Uppsala University, Disciplinary Domain of Science and Technology, Technology, Department of Engineering Sciences, Solid State Electronics.
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2013 (English)In: 2013 8th European Microwave Integrated Circuits Conference Proceedings, 2013, 53-56 p.Conference paper, Oral presentation with published abstract (Refereed)
Abstract [en]

Generating high output power at radio frequencies in CMOS becomes more challenging as technology is scaled. Limitations mainly come from device design. We demonstrate the feasibility of an 10 V LDMOS device fabricated in 65 nm foundry CMOS technology with no added process steps or mask. DC, RF, and power characterization are presented which show the feasibility of the device. The LDMOS device is used in an integrated WLAN-PA design and 32.8 dBm linear output power in the 2.45 GHz band is achieved. Load-pull data also shows high output power capability at 5.8 GHz. The concept can also be used at 45 nm and 28 nm nodes in most foundry CMOS processes.

Place, publisher, year, edition, pages
2013. 53-56 p.
National Category
Engineering and Technology
Research subject
Engineering Science with specialization in Electronics
Identifiers
URN: urn:nbn:se:uu:diva-209603ISBN: 978-2-87487-032-3 (print)OAI: oai:DiVA.org:uu-209603DiVA: diva2:658678
Conference
European Microwave Integrated Circuits Conference (EuMIC)
Available from: 2013-10-22 Created: 2013-10-22 Last updated: 2014-02-10Bibliographically approved
In thesis
1. Design and Characterization of RF-LDMOS Transistors and Si-on-SiC Hybrid Substrates
Open this publication in new window or tab >>Design and Characterization of RF-LDMOS Transistors and Si-on-SiC Hybrid Substrates
2014 (English)Doctoral thesis, comprehensive summary (Other academic)
Abstract [en]

With increasing amount of user data and applications in wireless communication technology, demands are growing on performance and fabrication costs. One way to decrease cost is to integrate the building blocks in an RF system where digital blocks and high power amplifiers then are combined on one chip. This thesis presents LDMOS transistors integrated in a 65 nm CMOS process without adding extra process steps or masks. High power performance of the LDMOS is demonstrated for an integrated WLAN-PA design at 2.45 GHz with 32.8 dBm output power and measurements also showed that high output power is achievable at 5.8 GHz. For the first time, this kind of device is moreover demonstrated at X-band with over 300 mW/mm output power, targeting communication and radar systems at 8 GHz. As SOI is increasing in popularity due to better device performance and RF benefits, the buried oxide can cause thermal problems, especially for high power devices. To deal with self-heating effects and decrease the RF substrate losses further, this thesis presents a hybrid substrate consisting of silicon on top of polycrystalline silicon carbide (Si-on-poly-SiC). This hybrid substrate utilizes the high thermal conductivity of poly-SiC to reduce device self-heating and the semi-insulating properties to reduce RF losses. Hybrid substrates were successfully fabricated for the first time in 150 mm wafer size by wafer bonding and evaluation was performed in terms of both electrical and thermal measurements and compared to a SOI reference. Successful LDMOS transistors were fabricated for the first time on this type of hybrid substrate where no degradation in electrical performance was seen comparing the LDMOS to identical transistors on the SOI reference. Measurements on calibrated resistors showed that the thermal conductivity was 2.5 times better for the hybrid substrate compared to the SOI substrate. Moreover, RF performance of the hybrid substrate was investigated and the semi-insulating property of poly-SiC showed to be beneficial in achieving a high equivalent substrate parallel resistance and thereby low substrate losses. In a transistor this would be equal to better efficiency and output power. In terms of integration, the hybrid substrate also opens up the possibility of heterogeneous integration where silicon devices and GaN devices can be fabricated on the same chip.

Place, publisher, year, edition, pages
Uppsala: Acta Universitatis Upsaliensis, 2014. 58 p.
Series
Digital Comprehensive Summaries of Uppsala Dissertations from the Faculty of Science and Technology, ISSN 1651-6214 ; 1113
Keyword
LDMOS, RF, losses, crosstalk, silicon carbide, Si-on-SiC hybrid substrate, wafer bonding, CMOS
National Category
Engineering and Technology Other Electrical Engineering, Electronic Engineering, Information Engineering
Research subject
Engineering Science with specialization in Electronics
Identifiers
urn:nbn:se:uu:diva-215390 (URN)978-91-554-8852-9 (ISBN)
Public defence
2014-02-28, Häggsalen, Ångströmlaboratoriet, Lägerhyddsvägen 1, Uppsala, 09:30 (English)
Opponent
Supervisors
Available from: 2014-02-07 Created: 2014-01-13 Last updated: 2014-02-10

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Lotfi, SaraVestling, LarsNorström, HansOlsson, Jörgen

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