TLC: A tag-less cache for reducing dynamic first level cache energy
2013 (English)In: Proceedings of the 46th International Symposium on Microarchitecture, New York: ACM Press, 2013, 49-61 p.Conference paper (Refereed)
First level caches are performance-critical and are therefore optimized for speed. To do so, modern processors reduce the miss ratio by using set-associative caches and optimize latency by reading all ways in parallel with the TLB and tag lookup. However, this wastes energy since only data from one way is actually used.
To reduce energy, phased-caches and way-prediction techniques have been proposed wherein only data of the matching/predicted way is read. These optimizations increase latency and complexity, making them less attractive for first level caches.
Instead of adding new functionality on top of a traditional cache, we propose a new cache design that adds way index information to the TLB. This allow us to: 1) eliminate ex-tra data array reads (by reading the right way directly), 2) avoid tag comparisons (by eliminating the tag array), 3) later out misses (by checking the TLB), and 4) amortize the TLB lookup energy (by integrating it with the way information). In addition, the new cache can directly replace existing caches without any modication to the processor core or software.
This new Tag-Less Cache (TLC) reduces the dynamic energy for a 32 kB, 8-way cache by 60% compared to a VIPT cache without aecting performance.
Place, publisher, year, edition, pages
New York: ACM Press, 2013. 49-61 p.
Computer Engineering Computer Systems
IdentifiersURN: urn:nbn:se:uu:diva-213236DOI: 10.1145/2540708.2540714ISBN: 978-1-4503-2638-4OAI: oai:DiVA.org:uu-213236DiVA: diva2:681389
MICRO-46; December 7-11, 2013; Davis, CA, USA