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Bounding Loop Iterations for Timing Analysis
Uppsala University, Teknisk-naturvetenskapliga vetenskapsområdet, Mathematics and Computer Science, Department of Information Technology.
1998 (English)In: IEEE Real-Time Applications Symposium; RTAS'98, 1998Conference paper (Refereed)
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Keyword [en]
WCET, Static Analysis, Real-time systems
URN: urn:nbn:se:uu:diva-40707OAI: oai:DiVA.org:uu-40707DiVA: diva2:68608
Available from: 2008-10-17 Created: 2008-10-17

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