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Power Performance of 65 nm CMOS Integrated LDMOS Transistors at WLAN and X-band Frequencies
Uppsala University, Disciplinary Domain of Science and Technology, Technology, Department of Engineering Sciences, Solid State Electronics.
Ferdinand-Braun Institut. (Leibniz-Institut fuer Hoechstfrequenztechnik)
Uppsala University, Disciplinary Domain of Science and Technology, Technology, Department of Engineering Sciences, Solid State Electronics.
2016 (English)In: International journal of microwave and wireless technologies, ISSN 1759-0795, E-ISSN 1759-0787, Vol. 8, no 2, 135-141 p.Article in journal (Refereed) Published
Abstract [en]

Laterally diffused metal oxide semiconductor (LDMOS) transistors with 10V breakdown voltage have been implemented in a 65nm Complementary metal oxide semiconductor (CMOS) process without extra masks or process steps. Radio frequency (RF) performance for Wireless local area network (WLAN) frequencies and in X-band at 8GHz is investigated by load-pull measurements in class AB operation for both 3.3 and 5V supply voltage. Results at 2.45GHz showed 290mW/mm output power density with 17dB linear gain and over 45% power added efficiency (PAE) at 4dB compression at a supply voltage of 5V. Furthermore, results in X-band at 8GHz show 8dB linear gain, 320mW/mm output power density and over 22% PAE at 4dB compression. Third-order intermodulation measurements at 8GHz revealed OIP3 of 18.9 and 21.9dBm at 3.3 and 5V, respectively. The transistors were also tested for reliability which showed no drift in quiescent current after 26h of DC stress while high-power RF stress showed only small extrapolated drift at 10 years in output power density. This is to the authors' knowledge the first time high output power density in X-band is demonstrated for integrated LDMOS transistors manufactured in a 65nm CMOS process without extra process steps.

Place, publisher, year, edition, pages
2016. Vol. 8, no 2, 135-141 p.
National Category
Communication Systems
Research subject
Engineering Science with specialization in Electronics
Identifiers
URN: urn:nbn:se:uu:diva-215334DOI: 10.1017/S1759078714001603ISI: 000370689000002OAI: oai:DiVA.org:uu-215334DiVA: diva2:686889
Available from: 2014-01-13 Created: 2014-01-13 Last updated: 2017-12-06Bibliographically approved
In thesis
1. Design and Characterization of RF-LDMOS Transistors and Si-on-SiC Hybrid Substrates
Open this publication in new window or tab >>Design and Characterization of RF-LDMOS Transistors and Si-on-SiC Hybrid Substrates
2014 (English)Doctoral thesis, comprehensive summary (Other academic)
Abstract [en]

With increasing amount of user data and applications in wireless communication technology, demands are growing on performance and fabrication costs. One way to decrease cost is to integrate the building blocks in an RF system where digital blocks and high power amplifiers then are combined on one chip. This thesis presents LDMOS transistors integrated in a 65 nm CMOS process without adding extra process steps or masks. High power performance of the LDMOS is demonstrated for an integrated WLAN-PA design at 2.45 GHz with 32.8 dBm output power and measurements also showed that high output power is achievable at 5.8 GHz. For the first time, this kind of device is moreover demonstrated at X-band with over 300 mW/mm output power, targeting communication and radar systems at 8 GHz. As SOI is increasing in popularity due to better device performance and RF benefits, the buried oxide can cause thermal problems, especially for high power devices. To deal with self-heating effects and decrease the RF substrate losses further, this thesis presents a hybrid substrate consisting of silicon on top of polycrystalline silicon carbide (Si-on-poly-SiC). This hybrid substrate utilizes the high thermal conductivity of poly-SiC to reduce device self-heating and the semi-insulating properties to reduce RF losses. Hybrid substrates were successfully fabricated for the first time in 150 mm wafer size by wafer bonding and evaluation was performed in terms of both electrical and thermal measurements and compared to a SOI reference. Successful LDMOS transistors were fabricated for the first time on this type of hybrid substrate where no degradation in electrical performance was seen comparing the LDMOS to identical transistors on the SOI reference. Measurements on calibrated resistors showed that the thermal conductivity was 2.5 times better for the hybrid substrate compared to the SOI substrate. Moreover, RF performance of the hybrid substrate was investigated and the semi-insulating property of poly-SiC showed to be beneficial in achieving a high equivalent substrate parallel resistance and thereby low substrate losses. In a transistor this would be equal to better efficiency and output power. In terms of integration, the hybrid substrate also opens up the possibility of heterogeneous integration where silicon devices and GaN devices can be fabricated on the same chip.

Place, publisher, year, edition, pages
Uppsala: Acta Universitatis Upsaliensis, 2014. 58 p.
Series
Digital Comprehensive Summaries of Uppsala Dissertations from the Faculty of Science and Technology, ISSN 1651-6214 ; 1113
Keyword
LDMOS, RF, losses, crosstalk, silicon carbide, Si-on-SiC hybrid substrate, wafer bonding, CMOS
National Category
Engineering and Technology Other Electrical Engineering, Electronic Engineering, Information Engineering
Research subject
Engineering Science with specialization in Electronics
Identifiers
urn:nbn:se:uu:diva-215390 (URN)978-91-554-8852-9 (ISBN)
Public defence
2014-02-28, Häggsalen, Ångströmlaboratoriet, Lägerhyddsvägen 1, Uppsala, 09:30 (English)
Opponent
Supervisors
Available from: 2014-02-07 Created: 2014-01-13 Last updated: 2014-02-10

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Lotfi, SaraOlsson, Jörgen

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