Investigating reliability and stress mechanisms of DC and large-signal stressed CMOS 65-nm RF-LDMOS by gate current characterization
2015 (English)In: IEEE transactions on device and materials reliability, ISSN 1530-4388, Vol. 15, no 2, 191-197 p.Article in journal (Refereed) Published
This paper presents reliability measurements under DC and large-signal conditions of an LDMOS transistor integrated in a 65 nm CMOS process. The gate current was measured with high resolution across the whole operation area with an atto-sense unit, and distinct behavior was seen in the gate current characteristics due to hot-carrier injection (HCI) and Fowler-Nordheim (FN) tunneling. Several bias points were chosen for DC stress of the transistor and degradation of important parameters in terms of RF operation were studied. Furthermore, the behavior from DC stress was compared to large-signal stress of the device in class AB where output power was monitored. Results show that operation at a supply voltage of 3.3 V shows no significant drift of transistor parameters while operation at 5 V shows increase in on-resistance but no changes in quiescent current or threshold voltage. These results are in coherence with what DC stress at quiescent bias points for class AB showed and may imply that DC stress measurements are sufficient in order to understand transistor reliability during RF operation.
Place, publisher, year, edition, pages
2015. Vol. 15, no 2, 191-197 p.
Physical Sciences Electrical Engineering, Electronic Engineering, Information Engineering
Research subject Engineering Science with specialization in Electronics
IdentifiersURN: urn:nbn:se:uu:diva-215335DOI: 10.1109/TDMR.2015.2413845ISI: 000356174400009OAI: oai:DiVA.org:uu-215335DiVA: diva2:686890